Developer Guide

Contents

Using High-bandwidth Memory with
Intel® MKL

To achieve maximum performance,
Intel® MKL
may use the memkind library (https://github.com/memkind/memkind), which enables controlling memory characteristics and partitioning the heap between different kinds of memory. By default
Intel® MKL
memory manager tries to allocate memory to Multi-Channel Dynamic Random Access Memory (MCDRAM) using the memkind library on the 2
nd
generation Intel® Xeon Phi™ product family (for more details of MCDRAM, see https://software.intel.com/en-us/articles/mcdram-high-bandwidth-memory-on-knights-landing-analysis-methods-tools). If allocation of memory to MCDRAM is not possible at the moment,
Intel® MKL
memory manager falls back to a regular system allocator.
By default the amount of MCDRAM available for
Intel® MKL
is unlimited. To control the amount of MCDRAM available for
Intel® MKL
, do either of the following:
  • Call
    mkl_set_memory_limit (MKL_MEM_MCDRAM,
    <limit_in_mbytes>
    )
  • Set the environment variable:
    • For the bash shell:
      MKL_FAST_MEMORY_LIMIT="
      <limit_in_mbytes>
      "
    • For a C shell (csh or tcsh):
      setenv MKL_FAST_MEMORY_LIMIT "
      <limit_in_mbytes>
      "
The setting of the limit affects all
Intel® MKL
functions, including user-callable memory functions such as
mkl_malloc
. Therefore, if an application calls
mkl_malloc
,
mkl_calloc
, or
mkl_realloc
, which always tries to allocate memory to MCDRAM, make sure that the limit is sufficient.
If you replace
Intel® MKL
memory management functions with your own functions (for details, seeRedefining Memory Functions),
Intel® MKL
uses your functions and does not work with the memkind library directly.
Optimization Notice
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.
Notice revision #20110804
This notice covers the following instruction sets: SSE2, SSE4.2, AVX2, AVX-512.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804