Developer Guide

Contents

Interaction with the Message-passing Interface

To improve performance of cluster applications, it is critical for
Intel® MKL
to use the optimal number of threads, as well as the correct thread affinity. Usually, the optimal number is the number of available cores per node divided by the number of MPI processes per node. You can set the number of threads using one of the available methods, described in Techniques to Set the Number of Threads .
If the number of threads is not set,
Intel® MKL
checks whether it runs under MPI provided by the Intel® MPI Library. If this is true, the following environment variables define
Intel® MKL
threading behavior:
  • I_MPI_THREAD_LEVEL
  • MKL_MPI_PPN
  • I_MPI_NUMBER_OF_MPI_PROCESSES_PER_NODE
  • I_MPI_PIN_MAPPING
  • OMPI_COMM_WORLD_LOCAL_SIZE
  • MPI_LOCALNRANKS
The threading behavior depends on the value of
I_MPI_THREAD_LEVEL
as follows:
  • 0 or undefined.
    Intel® MKL
    considers that thread support level of Intel MPI Library is
    MPI_THREAD_SINGLE
    and defaults to sequential execution.
  • 1, 2, or 3.
    This value determines
    Intel® MKL
    conclusion of the thread support level:
    • 1 -
      MPI_THREAD_FUNNELED
    • 2 -
      MPI_THREAD_SERIALIZED
    • 3 -
      MPI_THREAD_MULTIPLE
    In all these cases,
    Intel® MKL
    determines the number of MPI processes per node using the other environment variables listed and defaults to the number of threads equal to the number of available cores per node divided by the number of MPI processes per node.
Instead of relying on the discussed implicit settings, explicitly set the number of threads for
Intel® MKL
.
Optimization Notice
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.
Notice revision #20110804
This notice covers the following instruction sets: SSE2, SSE4.2, AVX2, AVX-512.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804