Developer Reference

Contents

MT19937

This is a Mersenne Twister pseudorandom number generator:
,
,
,                   
,                                     
,                
,
.
Matrix A (32x32) has the following format:
where the 32-bit vector
a = a
31
...
a
0
has the value
a
= 0x9908B0DF.
Mersenne Twister pseudorandom number generator MT19937 is a modification of twisted generalized feedback shift register generator [Matsum92], [Matsum94]. MT19937 has the period length of 2
19937
-1 and is 623-dimensionally equidistributed with up to 32-bit accuracy. These properties make the generator applicable for simulations in various fields of science and engineering. The initialization procedure is essentially the same as described in [MT2002]. The state of the generator is represented by 624 32-bit unsigned integer numbers.
Real Implementation (Single and Double Precision)
The output vector is the sequence of the floating-point values
u
0
,
u
1
, ...
Integer Implementation
The output vector of 32-bit integers
y
0
,
y
1
, ...
Stream Initialization by Function
vslNewStream
MT19937 generates the stream and initializes it specifying the input 32-bit unsigned integer parameter seed. The stream state, that is, the array of 624 32-bit integers
x
0
, ...,
x
623
, is initialized by the procedure described in [MT2002] and based on the seed value.
Stream Initialization of Function
vslNewStreamEx
MT19937 generates the stream and initializes it specifying the array the array
params[]
of
n
32-bit integers:
  1. If
    n
    ≥ 1, perform initialization as described in [MT2002] using array
    params[]
    on input.
  2. If
    n
    = 0, assume params[0] = 1,
    n
    = 1 and perform initialization as described in the previous item.
Subsequences Selection Methods
vslSkipAheadStream
Supported
vslSkipAheadStreamEx
Not supported
vslLeapfrogStream
Not supported
Skip-ahead method supported by MT19937 is based on algorithms described in [Haram08].
Generator Period
Empirical Testing Results Summary
Test Name
vsRngUniform
vdRngUniform
viRngUniform
viRngUniformBits
3D Spheres Test
OK (0% errors) 
OK (0% errors) 
Not applicable
OK (0% errors) 
Birthday Spacing Test
Not applicable
Not applicable
Not applicable
OK (10% errors) 
Bitstream Test
Not applicable
Not applicable
Not applicable
OK (10% errors) 
Rank of 31x31 Binary Matrices Test
Not applicable
Not applicable
Not applicable
OK (10% errors) 
Rank of 32x32 Binary Matrices Test
Not applicable
Not applicable
Not applicable
OK (0% errors) 
Rank of 6x8 Binary Matrices Test
Not applicable
Not applicable
Not applicable
OK (0% errors) 
Counts-the-1’s Test (stream of bits)
Not applicable
Not applicable
Not applicable
OK (20% errors) 
Counts-the-1’s Test (stream of specific bytes)
Not applicable
Not applicable
Not applicable 
OK (0% errors) 
Craps Test
OK (30% errors) 
OK (30% errors) 
OK (30% errors) 
OK (30% errors) 
Parking Lot Test
OK (0% errors) 
OK (0% errors) 
Not applicable 
OK (0% errors) 
2D Self-Avoiding Random Walk Test
OK (0% errors) 
OK (10% errors) 
Not applicable
OK (10% errors) 
Note
  1. The tabulated data is obtained using the one-level (threshold) testing technique. The OK result indicates FAIL < 50%. The run fails when p-value falls outside the interval [0.05, 0.95].
  2. The stream tested is generated by calling the function
    vslNewStream
    with seed=7,777,777. 

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804