Developer Guide

Contents

Specifying Function Names

In the file with the list of functions for your custom
DLL
, adjust function names to the required interface. For example,
you can list the cdecl entry points as follows:
DGEMM
DTRSM
DDOT
DGETRF
DGETRS
cblas_dgemm
cblas_ddot
You can list the stdcall entry points as follows:
_DGEMM@60
_DDOT@20
_DGETRF@24
For more examples, see domain-specific lists of function
names
in the
<mkl directory>
\
tools
\
builder
folder.
This folder contains lists of function names for both cdecl or stdcall interfaces.
The lists of function
names
are provided in the
<mkl directory>
\
tools
\
builder
folder merely as examples. See Composing a List of Functions for how to compose lists of functions for your custom
DLL
.
Names of Fortran-style routines (BLAS, LAPACK, etc.) can be both upper-case or lower-case, with or without the trailing underscore. For example, these names are equivalent:
BLAS:
dgemm
,
DGEMM
,
dgemm_
,
DGEMM_
LAPACK:
dgetrf
,
DGETRF
,
dgetrf_
,
DGETRF_.
Properly capitalize names of C support functions in the function list. To do this, follow the guidelines below:
  1. In the
    mkl_service.h
    include file, look up a
    #define
    directive for your function
    (
    mkl_service.h
    is included in the
    mkl.h
    header file).
  2. Take the function name from the replacement part of that directive.
For example, the
#define
directive for the
mkl_disable_fast_mm
function is
#define mkl_disable_fast_mm MKL_Disable_Fast_MM
.
Capitalize the name of this function in the list like this:
MKL_Disable_Fast_MM
.
For the names of the Fortran support functions, see the tip.
Optimization Notice
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.
Notice revision #20110804
This notice covers the following instruction sets: SSE2, SSE4.2, AVX2, AVX-512.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804