Developer Guide

Contents

Instruction Set Specific Dispatching on Intel® Architectures

Intel® MKL
automatically queries and then dispatches the code path supported on your Intel® processor to the optimal instruction set architecture (ISA) by default. The
MKL_ENABLE_INSTRUCTIONS
environment variable or the
mkl_enable_instructions
support function enables you to dispatch to an ISA-specific code path of your choice. For example, you can run the Intel® Advanced Vector Extensions (Intel® AVX) code path on an Intel processor based on Intel® Advanced Vector Extensions 2 (Intel® AVX2), or you can run the Intel® Streaming SIMD Extensions 4.2 (Intel® SSE4.2) code path on an Intel AVX-enabled Intel processor. This feature is not available on non-Intel processors.
In some cases
Intel® MKL
also provides support for upcoming architectures ahead of hardware availability, but the library does not automatically dispatch the code path specific to an upcoming ISA by default. If for your exploratory work you need to enable an ISA for an Intel processor that is not yet released or if you are working in a simulated environment, you can use the
MKL_ENABLE_INSTRUCTIONS
environment variable or
mkl_enable_instructions
support function.
The following table lists possible values of
MKL_ENABLE_INSTRUCTIONS
alongside the corresponding ISA supported by a given processor.
MKL_ENABLE_INSTRUCTIONS
dispatches to the default ISA if the ISA requested is not supported on the particular Intel processor. For example, if you request to run the Intel AVX512 code path on a processor based on Intel AVX2,
Intel® MKL
runs the Intel AVX2 code path. The table also explains whether the ISA is dispatched by default on the processor that supports this ISA.
Value of
MKL_ENABLE_INSTRUCTIONS
ISA
Dispatched by Default
AVX512
Intel® Advanced Vector Extensions (Intel® AVX-512) for systems based on Intel® Xeon® processors
Yes
AVX512_E1
Intel® Advanced Vector Extensions (Intel® AVX-512) with support for Vector Neural Network Instructions.
Yes
AVX512_E2
ICX: Intel® Advanced Vector Extensions (Intel® AVX-512) enabled processors.
Yes
AVX512_MIC
Intel® Advanced Vector Extensions (Intel® AVX-512) for systems based on Intel® Xeon Phi™ processors
Yes
AVX512_MIC_E1
Intel® Advanced Vector Extensions 512 (Intel® AVX-512) for Intel® Many Integrated Core Architecture (Intel® MIC Architecture) with support for AVX512_4FMAPS and AVX512_4VNNIW instruction groups enabled processors
Yes
AVX2
Intel® AVX2
Yes
AVX
Intel® AVX
Yes
SSE4_2
Intel® SSE4.2
Yes
For more details about the
mkl_enable_instructions
function, including the argument values, see the
Intel® MKL
Developer Reference
.
For example:
  • To turn on automatic CPU-based dispatching of Intel AVX-512 with support of AVX512_4FMAPS and AVX512_4VNNI instruction groups on systems based on Intel Xeon Phi processors, do one of the following:
    • Call
      mkl_enable_instructions(MKL_ENABLE_AVX512_MIC_E1)
    • Set the environment variable:
      set MKL_ENABLE_INSTRUCTIONS=AVX512_MIC_E1
  • To configure the library not to dispatch more recent architectures than Intel AVX2, do one of the following:
    • Call
      mkl_enable_instructions(MKL_ENABLE_AVX2)
    • Set the environment variable:
      set MKL_ENABLE_INSTRUCTIONS=AVX2
Settings specified by the
mkl_enable_instructions
function take precedence over the settings specified by the
MKL_ENABLE_INSTRUCTIONS
environment variable.
Optimization Notice
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.
Notice revision #20110804
This notice covers the following instruction sets: SSE2, SSE4.2, AVX2, AVX-512.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804