• 2019 Update 7
  • 03/31/2020

Running an MPI/OpenMP* Program

Intel® MPI Library Developer Guide for Linux* OS
To run a hybrid MPI/OpenMP* program, follow these steps:
  1. Make sure the thread-safe (debug or release, as desired) Intel® MPI Library configuration is enabled (release is the default version). To switch to such a configuration, source
    with the appropriate argument, see Selecting Library Configuration for details. For example:
    $ source mpivars.sh release
  2. Set the
    environment variable to specify the desired process pinning scheme. The recommended value is
    $ export I_MPI_PIN_DOMAIN=omp
    This sets the process pinning domain size to be equal to
    . Therefore, if for example
    is equal to
    , each MPI process can create up to four threads within the corresponding domain (set of logical processors). If
    is not set, each node is treated as a separate domain, which allows as many threads per MPI process as there are cores.
  3. Note
    For pinning OpenMP* threads within the domain, use the Intel® compiler
    environment variable. See the Intel compiler documentation for more details.
  4. Run your hybrid program as a regular MPI program. You can set the
    variables directly in the launch command. For example:
    $ mpirun -n 4 -genv OMP_NUM_THREADS=4 -genv I_MPI_PIN_DOMAIN=omp ./myprog

See Also

Intel® MPI Library Developer Reference, section
Tuning Reference > Process Pinning > Interoperability with OpenMP*

Product and Performance Information


Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

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