Main ThreadProcess Pinning
Use this feature to pin a particular MPI
to a corresponding set of CPUs within a
node and avoid undesired
migration. This feature is available on
operating systems that provide the necessary kernel interfaces.
The following schemes are used to identify logical processors in a system:
System-defined logical enumeration
Topological enumeration based on three-level hierarchical identification
through triplets (package/socket, core, thread)
The number of a logical CPU is defined as the corresponding position
this CPU bit in the kernel affinity bit-mask. Use the
utility, provided with your Intel MPI Library installation
to find out the logical CPU
The three-level hierarchical identification uses
triplets that provide information about processor location and their order.
The triplets are hierarchically ordered (package, core, and thread).
See the example for one possible processor numbering
where there are
two sockets, four cores (two cores per socket), and
eight logical processors (two processors per core).
Logical and topological enumerations are not the
identify the correspondence between the logical and topological enumerations.
See Processor Information
for more details.
is not specified and
one of the sockets (NUMA-nodes) is not used, for better
performance the 'bunch' order will automatically be used instead
of the default ‘compact’ order.
If hyperthreading is on, the number or
processes on the node is greater than the number of cores and no
one process pinning environment variable is set. For better
performance, the "spread" order will automatically be used
instead of the default "compact" order.