Developer Reference

  • 2020
  • 10/23/2020
  • Public Content


Provides information on processors used in the system.
cpuinfo [[-]<options>]
Sequence of one-letter options. Each option controls a specific part of the output data.
General information about single cluster node shows:
  • the processor product name
  • the number of packages/sockets on the node
  • core and threads numbers on the node and within each package
  • SMT mode enabling
Logical processors identification table identifies threads, cores, and packages of each logical processor accordingly.
  • Processor
    - logical processor number.
  • Thread
    - unique processor identifier within a core.
  • Core
    - unique core identifier within a package.
  • Package
    - unique package identifier within a node.
Node decomposition table shows the node contents. Each entry contains the information on packages, cores, and logical processors.
  • Package Id
    - physical package identifier.
  • Cores Id
    - list of core identifiers that belong to this package.
  • Processors Id
    - list of processors that belong to this package. This list order directly corresponds to the core list. A group of processors enclosed in brackets belongs to one core.
Cache sharing by logical processors shows information of sizes and processors groups, which share particular cache level.
  • Size - cache size in bytes.
  • Processors - a list of processor groups enclosed in the parentheses those share this cache or no sharing otherwise.
Microprocessor signature hexadecimal fields (Intel platform notation) show signature values:
  • extended family
  • extended model
  • family
  • model
  • type
  • stepping
Microprocessor feature flags indicate what features the microprocessor supports. The Intel platform notation is used.
Table shows the following information about NUMA nodes:
  • NUMA Id
    - NUMA node identifier.
  • Processors
    - a list of processors in this node.
If the node has no processors, the node is not shown.
Equivalent to
Default sequence
Utility usage info
utility prints out the processor architecture information that can be used to define suitable process pinning settings. The output consists of a number of tables. Each table corresponds to one of the single options listed in the arguments table.
The architecture information is available on systems based on the Intel® 64 architecture.
utility is available for both Intel microprocessors and non-Intel microprocessors, but it may provide only partial information about non-Intel microprocessors.
An example of the
$ cpuinfo -gdcs
===== Processor composition ===== Processor name : Intel(R) Xeon(R) X5570 Packages(sockets) : 2 Cores : 8 Processors(CPUs) : 8 Cores per package : 4 Threads per core : 1 ===== Processor identification ===== Processor Thread Id. Core Id. Package Id. 0 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 0 2 0 5 0 2 1 6 0 3 0 7 0 3 1 ===== Placement on packages ===== Package Id. Core Id. Processors 0 0,1,2,3 0,2,4,6 1 0,1,2,3 1,3,5,7 ===== Cache sharing ===== Cache Size Processors L1 32 KB no sharing L2 256 KB no sharing L3 8 MB (0,2,4,6)(1,3,5,7) ===== Processor Signature ===== _________ ________ ______ ________ _______ __________ | xFamily | xModel | Type | Family | Model | Stepping | |_________|________|______|________|_______|__________| | 00 | 1 | 0 | 6 | a | 5 | |_________|________|______|________|_______|__________|

Product and Performance Information


Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804