Access HLD FPGA Reports in JSON Format
In addition to the
report.html
file, DPC++ also provides the HLD FPGA report data in JSON files.
The JSON files containing the HLD FPGA report data are available in the
<project_dir>/reports/lib/json
directory. The directory provides the following .json
files:
File
| Description
|
|---|---|
area.json | Area Analysis of System
|
block.json | Block view of the System Viewer
|
bottleneck.json | Bottleneck view of the Loop Analysis report |
gmv.json | Global memory view of the System Viewer
|
info.json | Summary of project name, compilation command, versions, and timestamps |
loops.json | Navigation tree of the Loop Analysis report
|
loops_attr.json | Loop Analysis
|
mav.json | System view of the System Viewer
|
new_lmv.json | Kernel Memory Viewer
|
pipeline.json | Cluster view of the System Viewer
|
quartus.json | Intel® Quartus® Prime compilation summary
|
schedule.json | Schedule Viewer
|
summary.json | Kernel compilation name mapping
|
tree.json | Navigation tree of the System Viewer
|
warnings.json
| Compilation warning messages
|
You can read the following
.json
files without a special parser:
- area.json
- area_src.json
- loops.json
- quartus.json
- summary.json
For example, if you want to identify all the values and bottlenecks for the initiation interval (II) of a loop, you can find the information in the
children
section in the loops.json
file, as shown below:
"name":"<block name|Kernel: kernel name> # Find the loops which do not begin with "Kernel:" "data":[<Yes|No>, <#|n/a>, <II|n/a>] # The data field corresponds to "Pipelined", "II", "Bottleneck"