Developer Guide

Contents

Access HLD FPGA Reports in JSON Format

In addition to the 
report.html
 file, DPC++ also provides the HLD FPGA report data in JSON files.
The JSON files containing the HLD FPGA report data are available in the
<project_dir>/reports/lib/json
 directory. The directory provides the following 
.json
 files:
JSON Files in the
<project_dir>/reports/lib/json
Directory
File
Description
area.json
Area Analysis of System
info.json
Summary
new_lmv.json
Memory Viewer
loops.json
Loops Analysis
mav.json
System View of Graph Viewer
quartus.json
Summary
summary.json
Summary
warnings.json
Summary
block.json
Block View of the Graph Viewer
pipeline.json
Cluster View of the Graph Viewer
You can read the following 
.json
 files without a special parser:
  • area.json
  • loops.json
  • quartus.json
  • summary.json
For example, if you want to identify all the values and bottlenecks for the initiation interval (II) of a loop, you can find the information in the 
children
 section in the 
loops.json
 file, as shown below:
"name":"<block name|Kernel: kernel name> # Find the loops which do not begin with "Kernel:" "data":[<Yes|No>, <#|n/a>, <II|n/a>] # The data field corresponds to "Pipelined", "II", "Bottleneck"

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserverd for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804