Intel® oneAPI DPC++ FPGA Optimization Guide

Developer Guide

Contents

Instrument the Kernel Pipeline with Performance Counters (
-Xsprofile
)

Enable profiling during design compilation to add profiling counters to the SYCL kernel pipeline. To instrument the SYCL code with performance counters, add the
-Xsprofile
 flag to your compiler command.
  • Instrumenting the design with performance counters increases hardware resource utilization (that is, increases FPGA area use) and typically decreases performance.
  • Ensure that all kernel names are unique so that the dynamic profiler interprets the results correctly.
In large designs, the overhead from profiling can cause f
MAX
 degradation. It may also prevent the design from fitting on the chip due to the area overhead of the profiling counters.

Product and Performance Information

1

Performance varies by use, configuration and other factors. Learn more at www.Intel.com/PerformanceIndex.