Intel® oneAPI DPC++ FPGA Optimization Guide (Beta)

Developer Guide

Contents

Instrument the Kernel Pipeline with Performance Counters (
-Xsprofile
)

Enable profiling during design compilation to add profiling counters to the SYCL kernel pipeline. To instrument the SYCL code with performance counters, add the
-Xsprofile
 flag to your compiler command.
  • Instrumenting the design with performance counters increases hardware resource utilization (that is, increases FPGA area use) and typically decreases performance.
  • Ensure that all kernel names are unique so that the dynamicprofiler interprets the results correctly.
In large designs, the overhead from profiling can cause f
MAX
 degradation. It may also prevent the design from fitting on the chip due to the area overhead of the profiling counters.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserverd for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804