Developer Guide

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Measure Kernel Performance

The Profiler instruments and connects performance counters in a daisy chain throughout the pipeline generated for the kernel program. The host then reads data collected by these counters. For example, in PCI Express® (PCIe®)-based systems, the host reads the Profiler data over the PCIe interface.
Consider the following SYCLexample code:
// Vector Add Kernel h.single_task<VectorAdd>([=]() { for (int i = 0; i < kSize; ++i) { r[i] = a[i] + b[i]; } });
The profiler instruments the pipeline created from this design as shown in Figure 1. Performance counters are added to each load and store instruction, which are hooked together in a daisy chain that connects to the CRA interface..
Intel® FPGA Dynamic Profiler for DPC++: Performance Counters Instrumentation
Intel® FPGA Dynamic Profiler for DPC++: Performance Counters Instrumentation
Applications that use many pipes or memory accesses might stall frequently to enable the completion of memory transfers. The dynamic profiler collects various types of performance metrics such as stall, occupancy, idle, and bandwidth data at these points in the pipeline to help in identifying memory or pipe operations that create stalls.

Product and Performance Information

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Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804