Data written to a pipe using a pipe
call remains in the pipe as long as the kernel program remains loaded on the FPGA device. In other words, the data written to a pipe is persistent across work-groups and NDRange invocations. Data written by a work item to a pipe remains in that pipe until another work item reads from it. In addition, the sequence of data in a pipe always follows FIFO ordering, and the order is independent of the work item that performs the write or read operation.
Data in pipes is not persistent across multiple or different invocations of kernel programs that lead to FPGA device reprogramming, or between context, program, device, or platform releases, even if the compiler performs optimizations that avoid reprogramming operations on a device. For example, if you run a host program twice using the same FPGA image, or if a host program releases and reacquires a context, the data in the pipe may or may not persist across the operation. FPGA device reset operations might happen behind the scenes on object releases that may purge data in any pipes.