Developer Guide

Contents

I/O Pipes

An I/O pipe is a unidirectional (source or sink) connection to the hardware that may be connected to input or output features of an FPGA board. These features might include network interfaces, PCIe®, cameras, or other data capture or processing devices or protocols.
A source I/O device provides data that a SYCL kernel can read whereas a sink I/O device accepts data written by a SYCL kernel and sends it to the hardware device. A common use of I/O pipes is to interface to ethernet connections that interface directly with the FPGA. The source reads from the network and the sink writes to the network. This allows a SYCL kernel to process data from the network and resend it back to the network.
For testing purposes, you can use files on the disk as input or output devices, allowing you to debug using emulation or simulation for faster compilation.
To implement I/O pipes, follow these steps:
  1. Consult your board vendor documentation before you implement I/O pipes in your kernel program.
  2. Use a
    struct
    with a numeric
    id
    to define a
    kernel_readable_io_pipe
    or
    kernel_writable_io_pipe
    type to declare an I/O pipe to interface with hardware peripherals. These definitions are typically provided by a board vendor.
    • The numeric
      id
      value is the 0-origin index into the interfaces in the channels section of the
      board_spec.xml
      for the device.
    • The
      chan_id
      argument is necessary for simulation and it is the name of the I/O interface listed in the
      board_spec.xml
      file as shown in the following:
    <channels> <interface name="board" port="c1" type="streamsource" width="32" chan_id="c1"/> <interface name="board" port="c2" type="streamsink" width="32" chan_id="c2"/> </channels>
    Only channels marked type
    streamsource
    or
    streamsink
    are used for indexing.
  3. Implement the interface to hardware I/O pipes or files (emulator or simulator) by mapping the
    id
    variable, as shown in the following:
    // Specialize a pipe type struct read_io_pipe { static constexpr unsigned id = 0; }; struct write_io_pipe { static constexpr unsigned id = 1; }; // id 0 -> file name or channel name: "c1" for hardware, "0" for emulator, "c1" for simulation. using read_iopipe = sycl::INTEL::kernel_readable_io_pipe<read_io_pipe, unsigned, 4>; // id 1 -> file name or channel name: "c2" for hardware, "1" for emulator, "c2" for simulation. using write_iopipe = sycl::INTEL::kernel_writeable_io_pipe<write_io_pipe, unsigned, 3>;
    where:
    For Hardware
    id N
    is mapped to the channel (not file) in the associated hardware. For example:
    • id 0
      is mapped to the
      chan_id
      in the first interface defined.
    • id 1
      is mapped to the
      chan_id
      in the second interface defined, and so on.
    If there is no matching channel, an error is generated.
    For Emulator
    id N
    is mapped to a file named
    N
    , which means
    id 0
    is file
    0
    . This file is read or written by reading or writing to the associated I/O pipe.
    For Simulator
    id N
    is mapped to
    chan_id
    names in the
    board_spec.xml
    file supplied with the BSP (See channels). For example:
    • id 0
      is mapped to the
      chan_id
      in the first interface defined.
    • id 1
      is mapped to the
      chan_id
      in the second interface defined, and so on.
    If there is no matching channel, an error is generated.

The I/O Pipe Classes and Their Use

The I/O pipe APIs exposed by the FPGA implementations is equivalent to the following class declarations:
template <class name, class dataT, size_t min_capacity = 0> class kernel_readable_io_pipe { public: static dataT read(); // Blocking static dataT read(bool &success_code); // Non-blocking }; template <class name, class dataT, size_t min_capacity = 0> class kernel_writeable_io_pipe { public: static void write(dataT data); // Blocking static void write(dataT data, bool &success_code); // Non-blocking }
The following table describes the
template
parameters:
Template Parameters
Parameter
Description
name
The type that is the basis of an I/O pipe identification. It is may be provided by the device vendor or user-defined. The type must contain a
static constexpr unsigned
expression with name
id
, which is used to determine the hardware device referenced by the I/O pipe.
dataT
The type of data packet contained within an I/O pipe. This is the data type that is read during a successful pipe
read()
operation, or written during a successful pipe
write()
operation. The type must have a standard layout and be trivially copyable.
min_capacity
User-defined minimum number of words (in units of
dataT
) that an I/O pipe must be able to store without any being read out. The compiler may create an I/O pipe with a larger capacity due to performance considerations.
A data word in this context is the data type that the pipe contains (
dataT pipe template
argument).
Example Code for I/O Pipes
Here is an example that includes the definitions above:
// "Built-in pipes" provide interfaces with hardware peripherals // These definitions are typically provided by a device vendor and // made available to developers for use. namespace example_platform { template <unsigned ID> struct ethernet_pipe_id { static constexpr unsigned id = ID; }; using ethernet_read_pipe = kernel_readable_io_pipe<ethernet_pipe_id<0>, int, 0>; using ethernet_write_pipe = kernel_writeable_io_pipe<ethernet_pipe_id<1>, int, 0>; }

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804