Intel® oneAPI DPC++ FPGA Optimization Guide

Developer Guide

Contents

disable_loop_pipelining
 Attribute

If loop-carried dependencies result in an initiation interval (II) that is equal or close to the latency of a given iteration (effectively inducing serial execution of the pipelined loop), disable pipelining of the loop to generate a simpler datapath and reduce area utilization. Use the
disable_loop_pipelining
 attribute to direct the
Intel® oneAPI
DPC++/C++
 Compiler
 to disable pipelining of a loop. When you apply this attribute, the compiler generates a simple sequential loop datapath. This attribute applies to single work-item kernels (that is, single-threaded kernels) in which loops are pipelined. For more information about single work-item kernels and associated concepts, refer to Single Work-item Kernels.
Syntax
[[intel::disable_loop_pipelining]]
Unless otherwise specified, the compiler always attempts to generate a pipelined loop datapath where possible. When generating a pipelined circuit, resources of the loop must be duplicated to execute multiple iterations simultaneously, leading to an increased silicon area utilization. In cases where loop pipelining does not result in an improvement in throughput, avoid the area overhead by applying the
disable_loop_pipelining
 attribute to the loop, as shown in the following example code snippet:
Example
[[intel::disable_loop_pipelining]]
for (int i = 1; i < N; i++) {
  int j = a[i-1];
  // Memory dependency induces a high-latency loop feedback path
  a[i] = foo(j)
}
In the above example, the compiler fails to schedule the loop with a small II due to memory dependency (as reported in the Details pane of the Loop Analysis report). In such cases, loop pipelining is unlikely to be beneficial.

Product and Performance Information

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Performance varies by use, configuration and other factors. Learn more at www.Intel.com/PerformanceIndex.