Developer Guide

Contents

ii
Attribute

The initiation interval, or II, is the number of clock cycles between the launch of successive loop iterations.
Use the 
ii
 attribute to direct the 
Intel® oneAPI DPC++/C++ Compiler
to attempt to set the II for the loop that follows the attribute declaration. If the 
Intel® oneAPI DPC++/C++ Compiler
cannot achieve the specified II for the loop, then the compilation errors out.
Syntax
[[intelfpga::ii(n)]]
The 
ii
 attribute applies to pipelined loops in single task kernels. Refer to Pipelining for information about loop pipelining.
The attribute parameter
n
is required and must be a positive constant expression of integer type. The parameter specifies a minimum number of clock cycles to wait between the beginnings of execution of successive loop iterations.
The higher the II value, the longer the wait before the subsequent loop iteration starts executing. Refer to Loops Analysis for information about II and compiler reports that provide you with details on the performance implications of II on a specific loop.
The
ii
attribute should only be applied to a pipelined loop in a single work-item (task) kernel.
If the throughput of a loop is important to the overall throughput of your kernel, you can use the
ii
attribute to force an II value of 1 even though this may result in lower f
MAX
.
For some loops in your kernel, specifying a higher II value with the 
ii
 attribute than the value the compiler chooses by default can increase the maximum operating frequency (f
MAX
) of your kernel without a decrease in throughput.
A loop is a good candidate to have a higher 
ii
 than the default if the loop meets the following conditions:
  • The loop is not critical to the throughput of your kernel.
  • The running time of the loop is small compared to other loops it might contain.
Example
Consider a case where your kernel has two distinct pipelineable loops:
  • A short-running initialization loop that has a loop-carried dependence
  • A long-running loop that does the bulk of your processing.
In this case, the compiler does not know that the initialization loop has a much smaller impact on the overall throughput of your design. If possible, the compiler attempts to pipeline both loops with an II of 1.
Because the initialization loop has a loop-carried dependence, it does have a feedback path in the generated hardware. To achieve an II with such a feedback path, some clock frequency might be forfeited. Depending on the feedback path in the main loop, the rest of your design could have run at a higher operating frequency.
If you specify 
[[intelfpga::ii(2)]]
 on the initialization loop, then you are informing the compiler that it can be less aggressive in optimizing II for this loop. Less aggressive optimization allows the compiler to pipeline the path limiting the f
MAX
and allow your overall kernel design to achieve a higher f
MAX
.
The initialization loop takes longer to run with its new II. However, the decrease in the running time of the long-running loop due to higher f
MAX
 compensates for the increased length in running time of the initialization loop.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804