Developer Guide

Contents

ivdep
Attribute

Include the 
ivdep
 attribute in your single task kernel to assert that accesses to memory arrays do not cause loop-carried dependencies.
Syntax
[[intelfpga::ivdep]]
[[intelfpga::ivdep(safelen)]]
[[intelfpga::ivdep(array)]]
[[intelfpga::ivdep(array, safelen)]]
[[intelfpga::ivdep(safelen, array)]]
Applying the
ivdep
attribute incorrectly results in functionally incorrect hardware and potential functional differences between the hardware run and emulation. The
ivdep
attribute is in fact ignored in emulation.
During compilation, the 
Intel® oneAPI DPC++/C++ Compiler
creates hardware that ensures load and store instructions operate within dependency constraints. An example of a dependency constraint is that dependent load and store instructions must execute in order. The presence of the 
ivdep
 attribute instructs the
Intel® oneAPI DPC++/C++ Compiler
to remove the extra hardware between load and store instructions in the loop that immediately follows the attribute declaration in the kernel code. Removing the extra hardware may reduce logic utilization and lower the II value.
You can provide more information about loop dependencies by specifying a
safelen
parameter to the attribute by adding an integer type C++ constant expression argument to the attribute. The
safelen
parameter specifies the maximum number of consecutive loop iterations without loop-carried dependencies. For example,
[[intelfpga::ivdep(32)]]
indicates to the compiler that there are at least 32 iterations of the loop before loop-carried dependencies might be introduced. That is, while the
[[intelfpga::ivdep]]
attribute guarantees to the compiler that there are no implicit memory dependencies between any iteration of this loop,
[[intelfpga::ivdep(32)]]
guarantees that there does not exist a loop-carried dependence with a dependence distance less than 32. For example, if an iteration reads from memory, the preceding 32 iterations and succeeding 32 iterations are guaranteed not to write to the same memory location.
To specify that accesses to a particular memory array inside a loop do not cause loop-carried dependencies, add the array parameter to the attribute by specifying the array variable name as an argument to the attribute. The array specified by the 
ivdep
 attribute must be a local or private memory array, or a pointer variable that points to a global, local, or private memory storage. The array specified by the 
ivdep
 attribute can also be an array or a pointer member of a
struct
.
Examples
// No loop-carried dependencies for accesses to arrays A and B [[intelfpga::ivdep]] for (int i = 0; i < N; i++) { A[i] = A[i - X[i]]; B[i] = B[i - Y[i]]; } // No loop-carried dependencies for accesses to array A // Compiler inserts hardware that reinforces dependency constraints for B [[intelfpga::ivdep(A)]] for (int i = 0; i < N; i++) { A[i] = A[i - X[i]]; B[i] = B[i - Y[i]]; } // No loop-carried dependencies for array A inside struct [[intelfpga::ivdep(S.A)]] for (int i = 0; i < N; i++) { S.A[i] = S.A[i - X[i]]; } // No loop-carried dependencies for array A inside the struct pointed by S [[intelfpga::ivdep(S->X[2][3].A)]] for (int i = 0; i < N; i++) { S->X[2][3].A[i] = S.A[i - X[i]]; }
For additional information, refer to the FPGA tutorial sample "Loop IVDep" listed in the Intel® oneAPI Samples Browser on Linux* or Intel® oneAPI Samples Browser on Windows*.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804