Developer Guide

Contents

speculated_iterations
Attribute

Use the
speculated_iterations
attribute to direct the
Intel® oneAPI DPC++/C++ Compiler
to improve the performance of pipelined loops. The
speculated_iterations
attribute is applied to loops and hence, it must appear directly before the loop (the same place as other loop attributes). For more information, refer to Loop Speculation
Syntax
[[intelfpga::speculated_iterations(N)]]
where, the integer argument
N
specifies the permissible number of iterations to speculate.
The
Intel® oneAPI DPC++/C++ Compiler
generates hardware to run
N
extra iterations of the loop while ensuring the extra iterations do not affect anything. This allows either reducing the II of the loop or increasing the f
max
. The deciding factor is how quickly the exit condition of the loop is calculated. If the calculation takes many cycles, it is better to have larger
speculated_iterations
.
Extra iterations increase the time before the next invocation of the loop can begin. This may be a factor if the actual number of iterations of the loop is very small (less than 5 to 10 or similar). In this case, specify the
N
value as 0 to allow subsequent loop iterations to start immediately but at the cost of a larger II to allow more time to evaluate the exit condition. Refer to the Loop Analysis report in the
Intel® oneAPI DPC++ FPGA Optimization Guide
report to identify whether the exit condition is a bottleneck for II.
Example
[[intelfpga::speculated_iterations(1)]] while (m*m*m < N) { m += 1; } dst[0] = m;
The loop in this example will have one speculated iteration.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserverd for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804