Developer Guide

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Ignoring Dependencies Between Accessor Arguments

To direct the
Intel® oneAPI DPC++/C++ Compiler
to ignore dependencies between accessor arguments in a DPC++ kernel, add the
[[intel::kernel_args_restrict]]
attribute to your kernel. The
[[intel::kernel_args_restrict]]
attribute allows the compiler to analyze dependencies between kernel memory operations more accurately, which can result in higher performance. This attribute functions like the
-Xsno-accessor-aliasing
flag, which is no longer supported. However, you can apply the
[[intel::kernel_args_restrict]]
attribute at a more fine-grained level to individual kernels in the source code.
Example
#include <CL/sycl/INTEL/fpga_extensions.hpp> ... event event_restrict = device_queue.submit([&](handler& cgh) { // create accessors from global memory auto in_accessor = in_buf.template get_access<sycl_read>(cgh); auto out_accessor = restrict_out_buf.template get_access<sycl_write>(cgh); // run the task (note the use of the attribute here) cgh.single_task<KernelArgsRestrict>([=]() [[intel::kernel_args_restrict]] { for (unsigned i = 0; i < size; i++) { out_accessor[i] = in_accessor[i]; } }); }); ...
This attribute is an assurance to the compiler that accessors in the kernel arguments (and accessors derived from them) never point to the same memory location as any other accessor. It is up to you to ensure that this property is true.
For additional information, refer to the FPGA tutorial sample "Kernel Args Restrict" listed in the Intel® oneAPI Samples Browser on Linux* or Intel® oneAPI Samples Browser on Windows*.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804