Developer Guide


Disable Burst-Interleaving of Global Memory (

Intel® oneAPI DPC++/C++ Compiler
cannot burst-interleave global memory across different memory types. You can disable burst-interleaving for all global memory banks of the same type and manage them manually by including the
option in your
Manual partitioning of memory buffers overrides the default burst-interleaved configuration of global memory.
option requires a global memory type parameter. If you do not specify a memory type, the
Intel® oneAPI DPC++/C++ Compiler
issues an error message.
  • To direct the
    Intel® oneAPI DPC++/C++ Compiler
    to disable burst-interleaving for the default global memory, invoke the following command:
    dpcpp -fintelfpga -Xshardware <source_file>.cpp -Xsno-interleaving=default
  • Your accelerator board might include multiple global memory types. To identify the default global memory type, refer to board vendor's documentation for your Custom Platform.
  • For a heterogeneous memory system, to direct the
    Intel® oneAPI DPC++/C++ Compiler
    to disable burst-interleaving of a specific global memory type, perform the following tasks:
    1. Consult the
      file of your Custom Platform for the names of the available global memory types (for example, DDR and quad data rate (QDR)).
    2. To disable burst-interleaving for one of the memory types (for example, DDR), invoke:
      dpcpp -fintelfpga -Xshardware <source_file>.cpp -Xsno-interleaving=DDR
      Intel® oneAPI DPC++/C++ Compiler
      enables manual partitioning for the DDR memory bank and configures the other memory bank in a burst-interleaved fashion.
    3. To disable burst-interleaving for more than one type of global memory buffers, include a
      option for each global memory type. For example, to disable burst-interleaving for both DDR and QDR, invoke the following command:
      dpcpp -fintelfpga -Xshardware <source_file>.cpp -Xsno-interleaving=DDR -Xsno-interleaving=QDR
Do not pass a buffer as a kernel argument that associates it with multiple memory technologies.

Product and Performance Information


Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804