The maximum clock frequency at which a digital circuit can operate is called its f
. This is the maximum rate at which the outputs of registers are updated.
The physical propagation delay of the signal across combinational logic between two consecutive register stages limits the clock speed. This propagation delay is a function of the complexity of the combinational logic in the path.
The path with the most combinational logic elements (and the highest delay) limits the speed of the entire circuit. This speed limiting path is often referred to as the
is calculated as the inverse of the critical path delay. You may want to have high f
since it results in high performance in the absence of other bottlenecks.