Developer Guide

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Pipelining

Pipelining is a design technique used in synchronous digital circuits to increase f
MAX
. Pipelining involves adding registers to the critical path, which decreases the amount of logic between each register. Less logic takes less time to execute, which enables an increase in f
MAX
.
The critical path in a circuit is the path between any two consecutive registers with the highest latency. That is, the path between two consecutive registers where the operations take the longest to complete.
Pipelining is especially useful when processing a stream of data. A pipelined circuit can have different stages of the pipeline operating on different input stream data in the same clock cycle, which leads to better data processing throughput.

Example

Consider a simple circuit with operations A and B on the critical path. If operation A takes 5 ns to complete and operation B takes 15ns to complete, thenthe time delay on the critical path is 20 ns. This results in an f
MAX
 of 50 MHz (1/
max_delay
).
Unpipelined Logic Block with the f
MAX
of 50 MHz and Latency of Two Clock Cycles
Unpipelined Logic Block with the fMAX of 50 MHz and Latency of Two Clock Cycles
If a pipeline register is added between A and B, the critical path changes. The delay on the critical path is now 15ns. Pipelining this block results in an f
MAX
of 66.67 MHz, and the maximum delay between two consecutive registers is 15 ns.
Pipelined Logic Block with an f
MAX
of 66.67 MHz and Latency of Three clock cycles
Pipelined Logic Block with an fMAX of 100 MHz and Latency of Three clock cycles
While pipelining generally results in a higher f
MAX
, it increases latency. In the previous example, the latency of the block containing A and B increases from two to three clock cycles after pipelining.

Product and Performance Information

1

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Notice revision #20110804