Developer Guide

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Omit Hardware that Generates and Dispatches Kernel IDs

The
[[intelfpga::max_global_work_dim(0)]]
kernel attribute instructs the
Intel® oneAPI DPC++/C++ Compiler
to omit logic that generates and dispatches global, local, and group IDs into the compiled kernel.
Semantically, the
[[intelfpga::max_global_work_dim(0)]]
kernel attribute specifies that the global work dimension of the kernel is zero. Setting this kernel attribute means that the kernel does not use any global, local, or group IDs. The presence of this attribute in the kernel code serves as a guarantee to the compiler that the kernel is a single work-item kernel.
When compiling the following kernel, the compiler generates interface hardware as illustrated in Figure 1:
cgh.single_task<class kernelComputeAsTask>( [=]() [[intelfpga::max_global_work_dim(0)]] { for (unsigned i = 0; i < SIZE; i++) { accessorRes[i] = accessorIdx[i] * 2; } });
The
[[intelfpga::max_global_work_dim(0)]]
attribute must be run as a task and not as a
parallel_for
function.
Compiler-generated Interface Hardware for a Kernel with the
[[intelfpga::max_global_work_dim(0)]]
Attribute
If your current kernel implementation has multiple work-items but does not use global, local, or group IDs, you can use the
[[intelfpga::max_global_work_dim(0)]]
kernel attribute if you modify the kernel code accordingly:
  1. Wrap the kernel body in a
    for
    loop that iterates as many times as the number of work-items.
  2. Use
    cgh.single_task<kernelName>
    to invoke the device code.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804