Pipes provide a mechanism for passing data between kernels and synchronizing kernels with high efficiency and low latency. Pipes allow kernels to communicate directly with each other using on-device FIFO buffers that are implemented using FPGA memory resources. The
supports concurrent kernel execution by launching each kernel in a separate command queue. Using pipes for data movement between concurrently executing kernels allows for data transfer without waiting for kernel completion, which can significantly increase the throughput of your design. Refer to
for more details about how to use pipes in your device code.