Developer Guide

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Minimize the Memory Dependencies for Loop Pipelining

Intel® oneAPI DPC++/C++ Compiler
ensures that the memory accesses from the same thread respects the program order. When you compile an NDRange kernel, use barriers to synchronize memory accesses across threads in the same work-group.
Loop dependencies might introduce bottlenecks for single work-item kernels due to latency associated with the memory accesses. The
Intel® oneAPI DPC++/C++ Compiler
defers a memory operation until a dependent memory operation completes. This could affect the loop initiation interval (II). The
Intel® oneAPI DPC++/C++ Compiler
indicates the memory dependencies in the optimization report.
To minimize the impact of memory dependencies for loop pipelining:
  • Ensure that the
    Intel® oneAPI DPC++/C++ Compiler
    does not assume false dependencies.
  • When the static memory dependence analysis fails to prove that dependency does not exist, the
    Intel® oneAPI DPC++/C++ Compiler
    assumes that a dependency exists and modifies the kernel execution to enforce the dependency. The impact of the dependency enforcement is lower if the memory system is stall-free.
    • Write-after-read operations with data dependency on a load-store unit can take just two clock cycles (II=2). Other stall-free scenarios can take up to seven clock cycles.
    • The
      Intel® oneAPI DPC++/C++ Compiler
      can fully resolve the read-after-write (control dependency) operation.
  • Override the static memory dependence analysis by adding the line
    [[intelfpga::ivdep]]
    before the loop in your kernel code if you are sure that it carries no dependences. For more information, refer to ivdep Attribute

Product and Performance Information

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Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserverd for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804