Developer Guide


FPGA Kernel Attributes

The following table summarizes kernel attributes:
FPGA Kernel Attributes
[[intelfpga::max_work_group_size(Z, Y, X)]]
Specifies a maximum or the required work-group size for optimizing hardware use of the DPC++ kernel without involving excess logic.
[[intelfpga::max_work_group_size(1,1,MAX_WG_SIZE)]] { accessorRes[wiID] = accessorIdx[wiID] * 2; });
Omits logic that generates and dispatches global, local, and group IDs into the compiled kernel.
[[intelfpga::max_global_work_dim(0)]] { for (unsigned i = 0; i < SIZE; i++) { accessorRes[i] = accessorIdx[i] * 2; } }
Specifies the number of work items within a work group that the compiler executes in a SIMD or vectorized manner.
[[intelfpga::num_simd_work_items(NUM_SIMD_WORK_ITEMS), cl::reqd_work_group_size(1,1,REQD_WORK_GROUP_SIZE)]] { accessorRes[wiID] = sqrt(accessorIdx[wiID]); });

Product and Performance Information


Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserverd for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804