Developer Guide

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FPGA Kernel Attributes

The following table summarizes kernel attributes:
FPGA Kernel Attributes
Attribute
Description
Example
[[intel::scheduler_target_fmax_mhz(N)]]
Determines the pipelining effort the scheduler attempts during the scheduling process.
[[intel::scheduler_target_fmax_mhz(SCHEDULER_TARGET_FMAX)]] { for (unsigned i = 0; i < SIZE; i++) { accessorRes[0] += accessorIdx[i] * 2; } });
[[intel::max_work_group_size(Z, Y, X)]]
Specifies a maximum or the required work-group size for optimizing hardware use of the DPC++ kernel without involving excess logic.
[[intel::max_work_group_size(1,1,MAX_WG_SIZE)]] { accessorRes[wiID] = accessorIdx[wiID] * 2; });
[[intel::max_global_work_dim(0)]]
Omits logic that generates and dispatches global, local, and group IDs into the compiled kernel.
[[intel::max_global_work_dim(0)]] { for (unsigned i = 0; i < SIZE; i++) { accessorRes[i] = accessorIdx[i] * 2; } }
[[intel::num_simd_work_items(N)]
Specifies the number of work items within a work group that the compiler executes in a SIMD or vectorized manner.
[[intel::num_simd_work_items(NUM_SIMD_WORK_ITEMS), cl::reqd_work_group_size(1,1,REQD_WORK_GROUP_SIZE)]] { accessorRes[wiID] = sqrt(accessorIdx[wiID]); });
[[intel::no_global_work_offset(1)]]
Omits generating hardware required to support global work offsets.
[[intel::no_global_work_offset(1))]] { accessorRes[wiID] = accessorIdx[wiID] * 2; }
[[intel::kernel_args_restrict]]
Ignores the dependencies between accessor arguments in a DPC++ kernel.
[[intel::kernel_args_restrict]] { for (unsigned i = 0; i < size; i++) { out_accessor[i] = in_accessor[i]; } });

Product and Performance Information

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Performance varies by use, configuration and other factors. Learn more at www.Intel.com/PerformanceIndex.