FPGA Loop Directives
Pragma or Attribute
Intel® oneAPIto disable pipelining of a loop.
Forces a loop to have a loop initialization interval (II) of a specified value.
Ignores memory dependencies between iterations of this loop
Coalesces nested loops into a single loop without affecting the loop functionality.
Limits the number of iterations of a loop that can simultaneously execute at any time.
Maximizes the throughput and hardware resource occupancy of pipelined inner loops in a loop nest.
Improves the performance of pipelined loops.
Unrolls a loop in the kernel code.