Developer Guide

Contents

FPGA LSU Controls

The following table summarizes the load-store unit (LSU) control:
LSU Controls
Syntax
Description
Example
cl::sycl::INTEL::lsu<…>;
Allows you to specify LSU attributes to control the LSU inferred by the compiler.
No attributes attempt to infer a pipelined LSU.
For example:
  • INTEL::burst_coalesce<true>
  • INTEL::statically_coalesce<false>
  • INTEL::prefetch<true>
  • INTEL::cache<1024>
#include <CL/sycl/INTEL/fpga_extensions.hpp> using namespace sycl … using BurstCoalescedLSU = cl::sycl::INTEL::lsu<cl::sycl::INTEL::burst_coalesce<true>, cl::sycl::INTEL::statically_coalesce<false>>; BurstCoalescedLSU::store(output_ptr, X);

Product and Performance Information

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Performance varies by use, configuration and other factors. Learn more at www.Intel.com/PerformanceIndex.