Intel® oneAPI DPC++ FPGA Optimization Guide (Beta)

Developer Guide

Contents

FPGA Memory Attributes

The following table summarizes memory attributes:
FPGA Memory Attributes
Attribute
Description
Example
register
Forces a variable or an array to be carried through the pipeline in registers. 
// Array is implemented in register
[[intelfpga::register]] int array[128];
memory
Forces a variable or an array to be implemented as an embedded memory. 
// Array is implemented in memory (MLAB/M20K), 
// the actual implementation is automatically decided 
// by the compiler
[[intelfpga::memory]] int array1[128];

// Array is implemented in M20K
[[intelfpga::memory("BLOCK_RAM")]] int array2[64];

// Array is implemented in MLAB
[[intelfpga::memory("MLAB")]] int array3[64];
numbanks
Specifies that the memory implementing the variable or array must have a defined number of memory banks. 
// Array is implemented with 2 banks
[[intelfpga::numbanks(2)]] int array[128];
bank_bits
Specifies that the local memory addresses should use bits for bank selection, 
// Array is implemented with 4 banks where 
// bits 6 and 5 of the memory word address 
// are used to select between the banks
[[intelfpga::bank_bits(6,5)]] int array[128];
bankwidth
Specifies that the memory implementing the variable or array must have memory banks of a defined width. 
// Each  memory bank  is 8 bytes (64-bits) wide
[[intelfpga::bankwidth(8)]] int array[128];
singlepump
Specifies that the memory implementing the variable or array must be clocked at the same rate as the kernel accessing it. 
// Array is implemented in a memory that operates 
// at the same clock frequency as the kernel
[[intelfpga::singlepump]] int array[128];
doublepump
Specifies that the memory implementing the variable or an array must be clocked at twice the rate as the kernel accessing it. 
// Array is implemented in a memory that operates at 
// twice the clock frequency of the kernel
[[intelfpga::doublepump, bankwidth(128)]] int array[128];
private_copies
Specifies that the memory implementing the variable or an array has no more than the specified number of independent copies to enable concurrent thread or loop iteration accesses. 
// Array is implemented in a memory with two 
// private copies
[[intelfpga::private_copies(2)]] int array[128];
max_replicates
Specifies that the memory implementing the variable or an array has no more than the specified number of replicates to enable simultaneous accesses from the datapath. 
// Array is implemented in a memory with maximum four 
// replicates
[[intelfpga::max_replicates(4)]] int array[128];
simple_dual_port
Specifies that the memory implementing the variable or array should have no port that serves both reads and writes. 
// Array is implemented in a memory such that no 
// single port serves both a read and a write
[[intelfpga::simple_dual_port]] int array[128];
merge
Allows merging of two or more variables or arrays defined in the same scope with respect to width or depth. 
// Both arrays are merged width-wise and implemented 
// in the same memory system
[[intelfpga::merge("mem", "width")]] short arrayA[128];
[[intelfpga::merge("mem", "width")]] short arrayB[128];
force_pow2_depth
Specifies that the memory implementing the variable or array has a power-of-2 depth. 
// array1 is implemented in a memory with depth 1536
[[intelfpga::force_pow2_depth(0)]] int array1[1536];

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804