Version: : 2021.2
Last Updated: : 03/26/2021
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FPGA Memory Attributes

The following table summarizes memory attributes:

FPGA Memory Attributes
Attribute	Description	Example
bank_bits	Specifies that the local memory addresses should use bits for bank selection,	// Array is implemented with 4 banks where // bits 6 and 5 of the memory word address // are used to select between the banks [[intel::bank_bits(6,5)]] int array[128];
bankwidth	Specifies that the memory implementing the variable or array must have memory banks of a defined width.	// Each memory bank is 8 bytes (64-bits) wide [[intel::bankwidth(8)]] int array[128];
doublepump	Specifies that the memory implementing the variable, or an array must be clocked at twice the rate as the kernel accessing it.	// Array is implemented in a memory that operates at // twice the clock frequency of the kernel [[intel::doublepump, bankwidth(128)]] int array[128];
force_pow2_depth	Specifies that the memory implementing the variable or array has a power-of-2 depth.	// array1 is implemented in a memory with depth 1536 [[intel::force_pow2_depth(0)]] int array1[1536];
max_replicates	Specifies that the memory implementing the variable, or an array has no more than the specified number of replicates to enable simultaneous accesses from the datapath.	// Array is implemented in a memory with maximum four // replicates [[intel::max_replicates(4)]] int array[128];
memory	Forces a variable or an array to be implemented as an embedded memory.	// Array is implemented in memory (MLAB/M20K), // the actual implementation is automatically decided // by the compiler [[intel::fpga_memory]] int array1[128]; // Array is implemented in M20K [[intel::fpga_memory("BLOCK_RAM")]] int array2[64]; // Array is implemented in MLAB [[intel::fpga_memory("MLAB")]] int array3[64];
merge	Allows merging of two or more variables or arrays defined in the same scope with respect to width or depth.	// Both arrays are merged width-wise and implemented // in the same memory system [[intel::merge("mem", "width")]] short arrayA[128]; [[intel::merge("mem", "width")]] short arrayB[128];
numbanks	Specifies that the memory implementing the variable or array must have a defined number of memory banks.	// Array is implemented with 2 banks [[intel::numbanks(2)]] int array[128];
private_copies	Specifies that the memory implementing the variable, or an array has no more than the specified number of independent copies to enable concurrent thread or loop iteration accesses.	// Array is implemented in a memory with two // private copies [[intel::private_copies(2)]] int array[128];
register	Forces a variable or an array to be carried through the pipeline in registers.	// Array is implemented in register [[intel::fpga_register]] int array[128];
simple_dual_port	Specifies that the memory implementing the variable or array should have no port that serves both reads and writes.	// Array is implemented in a memory such that no // single port serves both a read and a write [[intel::simple_dual_port]] int array[128];
singlepump	Specifies that the memory implementing the variable or array must be clocked at the same rate as the kernel accessing it.	// Array is implemented in a memory that operates // at the same clock frequency as the kernel [[intel::singlepump]] int array[128];

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