Developer Guide


FPGA Optimization Flags

The following table summarizes FPGA optimization flags:
FPGA Optimization Flags
-Xsclock=<clock target in Hz/KHz/MHz/GHz or s/ms/us/ns/ps>
Schedules f
target for kernels.
dpcpp -fintelfpga –Xshardware –Xsclock=<clock target> <source_file>.cpp
Disables burst-interleaving for all global memory banks of the same type and manages them manually
dpcpp -fintelfpga -Xshardware <source_file>.cpp
Forces ring interconnect for global memory.
dpcpp -fintelfpga -Xshardware -Xsglobal-ring <source_file>.cpp
Narrows the interconnect to save area while limiting write-only throughput to one bank's worth.
dpcpp -fintelfpga -Xshardware -Xsforce-single-store-ring <source_file>.cpp
Narrows the interconnect to save area while reducing read-only throughput.
dpcpp -fintelfpga -Xshardware -Xsnum-reorder=1 <source_file>.cpp
Reduces kernel area use by removing kernel invocation queue in DPC++ kernel.
dpcpp -fintelfpga -Xshardware -Xsno-hardware-kernel-invocation-queue <source_file>.cpp
Modifies the handshaking protocol used in certain areas of the design
dpcpp -fintelfpga -Xshardware -Xshyper-optimized-handshaking=auto <source_file>.cpp
dpcpp -fintelfpga -Xshardware -Xshyper-optimized-handshaking=off <source_file>.cpp
Disables the automatic fusion of loops when compiling the design.
dpcpp -fintelfpga -Xshardware -Xsdisable-auto-loop-fusion <source_file>.cpp
Fuses adjacent loops with unequal trip counts into a single loop without affecting either loop's functionality.
dpcpp -fintelfpga -Xshardware -Xsenable-unequal-tc-fusion <source_file>.cpp
Pipelines loops in non-task (
) kernels.
dpcpp -fintelfpga –Xshardware -Xsauto-pipeline <
Removes intermediary floating-point rounding operations and conversions whenever possible and carries additional bits to maintain precision.
dpcpp -fintelfpga -Xshardware -Xsffp-contract=fast <source_file>.cpp

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