Developer Guide

Contents

FPGA Optimization Flags

The following table summarizes FPGA optimization flags:
FPGA Optimization Flags
Flags
Description
Example
-Xsclock=<clock target in Hz/KHz/MHz/GHz or s/ms/us/ns/ps>
Schedules f
MAX
target for kernels.
dpcpp -fintelfpga –Xshardware –Xsclock=<clock target> <source_file>.cpp
-Xsno-interleaving=<global_memory_type>
Disables burst-interleaving for all global memory banks of the same type and manages them manually
dpcpp -fintelfpga -Xshardware <source_file>.cpp
-Xsno-interleaving=DDR
-Xsglobal-ring
Forces ring interconnect for global memory.
dpcpp -fintelfpga -Xshardware -Xsglobal-ring <source_file>.cpp
-Xsforce-single-store-ring
Narrows the interconnect to save area while limiting write-only throughput to one bank's worth.
dpcpp -fintelfpga -Xshardware -Xsforce-single-store-ring <source_file>.cpp
-Xsnum-reorder
Narrows the interconnect to save area while reducing read-only throughput.
dpcpp -fintelfpga -Xshardware -Xsnum-reorder=1 <source_file>.cpp
-Xsfp-relaxed
Relaxes the order of arithmetic floating-point operations using a balanced tree hardware implementation.
dpcpp -fintelfpga -Xshardware -Xsfp-relaxed <source_file>.cpp
-Xsfpc
Removes intermediary floating-point rounding operations and conversions whenever possible and carries additional bits to maintain precision.
dpcpp -fintelfpga -Xshardware -Xsfpc <source_file>.cpp
-Xsno-hardware-kernel-invocation-queue
Reduces kernel area use by removing kernel invocation queue in DPC++ kernel.
dpcpp -fintelfpga -Xshardware -Xsno-hardware-kernel-invocation-queue <source_file>.cpp
-Xshyper-optimized-handshaking=<auto|off>
Modifies the handshaking protocol used in certain areas of the design
dpcpp -fintelfpga -Xshardware -Xshyper-optimized-handshaking=auto <source_file>.cpp
dpcpp -fintelfpga -Xshardware -Xshyper-optimized-handshaking=off <source_file>.cpp
-Xsdisable-auto-loop-fusion
Disables the automatic fusion of loops when compiling the design.
dpcpp -fintelfpga -Xshardware -Xsdisable-auto-loop-fusion <source_file>.cpp
-Xsenable-unequal-tc-fusion
Fuses adjacent loops with unequal trip counts into a single loop without affecting either loop's functionality.
dpcpp -fintelfpga -Xshardware -Xsenable-unequal-tc-fusion <source_file>.cpp

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804