Developer Reference for Intel® oneAPI Math Kernel Library - C

Developer Reference

  • 0.10
  • 10/21/2020
  • Public Content
Contents

Sparse BLAS Skyline Matrix Storage Format

The skyline storage format is important for the direct sparse solvers, and it is well suited for Cholesky or LU decomposition when no pivoting is required.
The skyline storage format accepted in
Intel® oneAPI Math Kernel Library
 can store only triangular matrix or triangular part of a matrix. This format is specified by two arrays:
values
 and
pointers
. The following table describes these arrays:
values
A scalar array. For a lower triangular matrix it contains the set of elements from each row of the matrix starting from the first non-zero element to and including the diagonal element. For an upper triangular matrix it contains the set of elements from each column of the matrix starting with the first non-zero element down to and including the diagonal element. Encountered zero elements are included in the sets.
pointers
An integer array with dimension
(
m
+1)
, where
m
 is the number of rows for lower triangle (columns for the upper triangle).
pointers
]
i
] -
pointers
[0]+1
 gives the index of element in
values
 that is first non-zero element in row (column)
i
. The value of
pointers
[
m
]
 is set to
nnz
+
pointers
[0]
, where
nnz
 is the number of elements in the array
values
.
For example, consider the matrix
C
:
The low triangle of the matrix
C
 given above can be stored as follows: 

				values  =  [ 1  -2   5   4  -4   0   2   7   8   0   0   -5 ]
				pointers = [ 0   1   3   4   8   12 ]
and the upper triangle of this matrix
C
 can be stored as follows: 

				values   = [ 1  -1   5  -3   0   4   6   7  4   0   -5 ]
				pointers = [ 0   1   3   6   8   11 ]
This storage format is supported by the NIST Sparse BLAS library [Rem05].
Note that the
Intel® oneAPI Math Kernel Library
 Sparse BLAS routines operating with the skyline storage format do not support general matrices.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804