Developer Reference

  • 0.9
  • 09/09/2020
  • Public Content

Limitations of the FFTW2 Interface to
Intel® oneAPI Math Kernel Library

The FFTW2 wrappers implement the functionality of only those FFTW functions that
Intel® oneAPI Math Kernel Library
can reasonably support. Other functions are provided as no-operation functions, whose only purpose is to satisfy link-time symbol resolution. Specifically, no-operation functions include:
  • Real-to-half-complex and respective backward transforms
  • Print plan functions
  • Functions for importing/exporting/forgetting wisdom
  • Most of the FFTW functions not covered by the original FFTW2 documentation
Because the
Intel® oneAPI Math Kernel Library
implementation of FFTW2 wrappers does not use plan and plan node structures declared in
, the behavior of an application that relies on the internals of the plan structures defined in that header file is undefined.
FFTW2 wrappers define plan as a set of attributes, such as strides, used to commit the
Intel® oneAPI Math Kernel Library
FFT descriptor structure. If an FFTW2 computational function is called with attributes different from those recorded in the plan, the function attempts to adjust the attributes of the plan and recommit the descriptor. So, repeated calls of a computational function with the same plan but different strides, distances, and other parameters may be performance inefficient.
Plan creation functions disregard most planner flags passed through the
parameter. These functions take into account only the following values of
    If this value of
    is supplied, the plan is marked so that computational functions using that plan ignore the parameters related to output (
    , and
    ). Unlike the original FFTW interface, the wrappers never use the
    parameter as a scratch space for in-place transforms.
    If this value of
    is supplied, the plan is marked read-only. An attempt to change attributes of a read-only plan aborts the application.
FFTW wrappers are generally not thread safe. Therefore, do not use the same plan in parallel user threads simultaneously.

Product and Performance Information


Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804