Developer Reference for Intel® oneAPI Math Kernel Library - C

Developer Reference

  • 0.10
  • 10/21/2020
  • Public Content
Contents

Real MPI FFTW

Real-to-Complex MPI FFTW Transforms

rfftwnd_mpi_plan rfftw2d_mpi_create_plan(MPI_Comm
comm
, int
nx
, int
ny
, fftw_direction
dir
, int
flags
);
rfftwnd_mpi_plan rfftw3d_mpi_create_plan(MPI_Comm
comm
, int
nx
, int
ny
, int
nz
, fftw_direction
dir
, int
flags
);
rfftwnd_mpi_plan rfftwnd_mpi_create_plan(MPI_Comm
comm
, int
dim
, int
*n
, fftw_direction
dir
, int
flags
);
void rfftwnd_mpi(rfftwnd_mpi_plan
p
, int
n_fields
, fftw_real
*local_data
, fftw_real
*work
, fftwnd_mpi_output_order
output_order
);
void rfftwnd_mpi_local_sizes(rfftwnd_mpi_plan
p
, int
*local_nx
, int
*local_x_start
, int
*local_ny_after_transpose
, int
*local_y_start_after_transpose
, int
*total_local_size
);
void rfftwnd_mpi_destroy_plan(rfftwnd_mpi_plan
plan
);
Argument restrictions
:
  • Supported values of
    flags
     are
    FFTW_ESTIMATE
     and
    FFTW_MEASURE
    . If any other value of
    flags
     is supplied, the wrapper library reports an error '
    CDFT error in wrapper: unknown flags
    '.
  • The only supported value of
    n_fields
     is 1.
  • Function
    rfftwnd_mpi_create_plan
     can be used for both one-dimensional and multi-dimensional transforms.
  • Both values of the
    output_order
     parameter are supported:
    FFTW_NORMAL_ORDER
     and
    FFTW_TRANSPOSED_ORDER
    .

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804