Multi-threaded FFTW
This section discusses multi-threaded FFTW wrappers only. MPI FFTW wrappers, available only with for the Linux* and Windows* operating systems, are described in
Intel® oneAPI Math Kernel Library
a separate
section
.
Unlike the original FFTW interface, every computational function in the FFTW2 interface to provides multithreaded computation by default, with the maximum number of threads permitted in FFT functions (see "Techniques to Set the Number of Threads" in Developer Guide). To limit the number of threads,
call the threaded FFTW computational functions:
Intel® oneAPI Math Kernel Library
Intel® oneAPI Math Kernel Library
void fftw_threads(int
nthreads
, fftw_plan
plan
, int
howmany
, fftw_complex
*in
, int
istride
, int
idist
, fftw_complex
*out
, int
ostride
, int
odist
);
void fftw_threads_one(int
nthreads
, rfftwnd_plan
plan
, fftw_complex
*in
, fftw_complex
*out
);
...
void rfftwnd_threads_real_to_complex( int
nthreads
, rfftwnd_plan
plan
, int
howmany
, fftw_real
*in
, int
istride
, int
idist
, fftw_complex
*out
, int
ostride
, int
odist
);
Compared to its non-threaded counterpart, every
threaded computational function has
threads_
as the second
part of its name and additional first parameter
nthreads
. Set
the
nthreads
parameter to the thread limit to ensure that the computation requires at most
that number of threads.
Optimization Notice
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Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.
Notice revision #20110804
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This notice covers the following instruction sets: SSE2, SSE4.2, AVX2, AVX-512.