Developer Reference

  • 0.9
  • 09/09/2020
  • Public Content
Contents

Appendix E:
Graph Basics

Many applications in data science and machine learning involve working with data represented as graphs. Graph themselves can be represented in a variety of ways which describe relations between graph vertices and edges. Often, a graph is represented as a sparse matrix
A
(which is called the adjacency matrix of the graph) of size
nxn
, where
n
equals the number of vertices in the graph and element (
i
,
j
) represents quantitive information about the link between vertex
i
and vertex
j
. Most of the graph algorithms can then be described in the language of linear algebra with matrices and vectors.
Basic concepts related to graph algorithms and their representation in the language of linear algebra are described in Graph Fundamentals and Graphs in Linear Algebra. Various storage schemes for sparse matrices are described in Sparse Matrix Storage Formats.
Optimization Notice
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.
Notice revision #20110804
This notice covers the following instruction sets: SSE2, SSE4.2, AVX2, AVX-512.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804