Developer Reference for Intel® oneAPI Math Kernel Library - C

Developer Reference

  • 0.9
  • 09/09/2020
  • Public Content
Contents

BLAS Level 2 Routines

This section describes BLAS Level 2 routines, which perform matrix-vector operations. The following table lists the BLAS Level 2 routine groups and the data types associated with them.
BLAS Level 2 Routine Groups and Their Data Types
Routine Groups
Data Types
Description
s, d, c, z
Matrix-vector product using a general band matrix
s, d, c, z
Matrix-vector product using a general matrix
s, d
Rank-1 update of a general matrix
c, z
Rank-1 update of a conjugated general matrix
c, z
Rank-1 update of a general matrix, unconjugated
c, z
Matrix-vector product using a Hermitian band matrix
c, z
Matrix-vector product using a Hermitian matrix
c, z
Rank-1 update of a Hermitian matrix
c, z
Rank-2 update of a Hermitian matrix
c, z
Matrix-vector product using a Hermitian packed matrix
c, z
Rank-1 update of a Hermitian packed matrix
c, z
Rank-2 update of a Hermitian packed matrix
s, d
Matrix-vector product using symmetric band matrix
s, d
Matrix-vector product using a symmetric packed matrix
s, d
Rank-1 update of a symmetric packed matrix
s, d
Rank-2 update of a symmetric packed matrix
s, d
Matrix-vector product using a symmetric matrix
s, d
Rank-1 update of a symmetric matrix
s, d
Rank-2 update of a symmetric matrix
s, d, c, z
Matrix-vector product using a triangular band matrix
s, d, c, z
Solution of a linear system of equations with a triangular band matrix
s, d, c, z
Matrix-vector product using a triangular packed matrix
s, d, c, z
Solution of a linear system of equations with a triangular packed matrix
s, d, c, z
Matrix-vector product using a triangular matrix
s, d, c, z
Solution of a linear system of equations with a triangular matrix

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804