Developer Reference for Intel® oneAPI Math Kernel Library - C

Developer Reference

  • 0.9
  • 09/09/2020
  • Public Content
Contents

cblas_?tpmv

Computes a matrix-vector product using a triangular packed matrix.

Syntax

void
cblas_stpmv
(
const
CBLAS_LAYOUT
Layout
,
const
CBLAS_UPLO
uplo
,
const
CBLAS_TRANSPOSE
trans
,
const
CBLAS_DIAG
diag
,
const
MKL_INT
n
,
const
float
*ap
,
float
*x
,
const
MKL_INT
incx
);
void
cblas_dtpmv
(
const
CBLAS_LAYOUT
Layout
,
const
CBLAS_UPLO
uplo
,
const
CBLAS_TRANSPOSE
trans
,
const
CBLAS_DIAG
diag
,
const
MKL_INT
n
,
const
double
*ap
,
double
*x
,
const
MKL_INT
incx
);
void
cblas_ctpmv
(
const
CBLAS_LAYOUT
Layout
,
const
CBLAS_UPLO
uplo
,
const
CBLAS_TRANSPOSE
trans
,
const
CBLAS_DIAG
diag
,
const
MKL_INT
n
,
const
void
*ap
,
void
*x
,
const
MKL_INT
incx
);
void
cblas_ztpmv
(
const
CBLAS_LAYOUT
Layout
,
const
CBLAS_UPLO
uplo
,
const
CBLAS_TRANSPOSE
trans
,
const
CBLAS_DIAG
diag
,
const
MKL_INT
n
,
const
void
*ap
,
void
*x
,
const
MKL_INT
incx
);
Include Files
  • mkl.h
Description
The
?tpmv
 routines perform one of the matrix-vector operations defined as
x
 :=
A
*
x
, or
x
 :=
A
'*
x
, or
x
 := conjg(
A
')*
x
,
where:
x
 is an
n
-element vector,
A
 is an
n
-by-
n
 unit, or non-unit, upper or lower triangular matrix, supplied in packed form.
Input Parameters
Layout
Specifies whether two-dimensional array storage is row-major (
CblasRowMajor
) or column-major (
CblasColMajor
).
uplo
Specifies whether the matrix
A
 is upper or lower triangular:
uplo
 =
CblasUpper
if
uplo
 =
CblasLower
, then the matrix is low triangular.
trans
Specifies the operation:
if
trans
=
CblasNoTrans
, then
x
 :=
A
*
x
;
if
trans
=
CblasTrans
, then
x
 :=
A
'*
x
;
if
trans
=
CblasConjTrans
, then
x
 := conjg(
A
')*
x
.
diag
Specifies whether the matrix
A
 is unit triangular:
if
diag
 =
CblasUnit
 then the matrix is unit triangular;
if
diag
 =
CblasNonUnit
, then the matrix is not unit triangular.
n
Specifies the order of the matrix
A
. The value of
n
 must be at least zero.
ap
Array, size at least
((
n
*(
n
 + 1))/2)
.
For
Layout
 =
CblasColMajor
:
Before entry with
uplo
 =
CblasUpper
, the array
ap
 must contain the upper triangular matrix packed sequentially, column-by-column, so that respectively, and so on. Before entry with
uplo
 =
CblasLower
ap
[0]
 contains
A
1, 1
,
ap
[1]
 and
ap
[2]
 contain
A
1, 2
 and
A
2, 2
, the array
ap
 must contain the lower triangular matrix packed sequentially, column-by-column, so that
ap
[0]
 contains
A
1, 1
,
ap
[1]
 and
ap
[2]
 contain
A
2, 1
 and
A
3, 1
 respectively, and so on. When
diag
 =
CblasUnit
, the diagonal elements of
a
 are not referenced, but are assumed to be unity.
For
Layout
 =
CblasRowMajor
:
Before entry with
uplo
 =
CblasUpper
, the array
ap
 must contain the upper triangular matrix packed sequentially, row-by-row,
ap
[0]
 contains
A
1, 1
,
ap
[1]
 and
ap
[2]
 contain
A
1, 2
 and
A
1, 3
 respectively, and so on.
Before entry with
uplo
 =
CblasLower
, the array
ap
 must contain the lower triangular matrix packed sequentially, row-by-row, so that
ap
[0]
 contains
A
1, 1
,
ap
[1]
 and
ap
[2]
 contain
A
2, 1
 and
A
2, 2
 respectively, and so on.
x
Array, size at least
(1 + (
n
 - 1)*abs(
incx
))
. Before entry, the incremented array
x
 must contain the
n
-element vector
x
.
incx
Specifies the increment for the elements of
x
.
The value of
incx
 must not be zero.
Output Parameters
x
Overwritten with the transformed vector
x
.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804