Developer Reference

  • 0.10
  • 10/21/2020
  • Public Content
Contents

Inspector-executor Sparse BLAS Analysis Routines

Analysis Routines and their Data Types
Routine or Function Group
Description
Provides and estimate of the number and type of upcoming calls to LU smoother functionality.
Provides estimate of number and type of upcoming matrix-vector operations.
Provides estimate of number and type of upcoming triangular system solver operations.
Provides estimate of number and type of upcoming matrix-matrix multiplication operations.
Provides estimate of number and type of upcoming triangular matrix solve with multiple right hand sides operations.
Sets estimate of the number and type of upcoming matrix-vector operations.
Sets estimate of number and type of upcoming
mkl_sparse_?_symgs
operations.
Provides memory requirements for performance optimization purposes.
Analyzes matrix structure and performs optimizations using the hints provided in the handle.
Optimization Notice
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.
Notice revision #20110804
This notice covers the following instruction sets: SSE2, SSE4.2, AVX2, AVX-512.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserverd for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804