Developer Reference for Intel® oneAPI Math Kernel Library - C

Developer Reference

  • 0.9
  • 09/09/2020
  • Public Content
Contents

mkl_sparse_?_create_csc

Creates a handle for a CSC format matrix.

Syntax

sparse_status_t mkl_sparse_s_create_csc
(
sparse_matrix_t
*A
,
const sparse_index_base_t
indexing
,
const MKL_INT
rows
,
const MKL_INT
cols
,
MKL_INT
*cols_start
,
MKL_INT
*cols_end
,
MKL_INT
*row_indx
,
float
*values
);
sparse_status_t mkl_sparse_d_create_csc
(
sparse_matrix_t
*A
,
const sparse_index_base_t
indexing
,
const MKL_INT
rows
,
const MKL_INT
cols
,
MKL_INT
*cols_start
,
MKL_INT
*cols_end
,
MKL_INT
*row_indx
,
double
*values
);
sparse_status_t mkl_sparse_c_create_csc
(
sparse_matrix_t
*A
,
const sparse_index_base_t
indexing
,
const MKL_INT
rows
,
const MKL_INT
cols
,
MKL_INT
*cols_start
,
MKL_INT
*cols_end
,
MKL_INT
*row_indx
,
MKL_Complex8
*values
);
sparse_status_t mkl_sparse_z_create_csc
(
sparse_matrix_t
*A
,
const sparse_index_base_t
indexing
,
const MKL_INT
rows
,
const MKL_INT
cols
,
MKL_INT
*cols_start
,
MKL_INT
*cols_end
,
MKL_INT
*row_indx
,
MKL_Complex16
*values
);
Include Files
  • mkl_spblas.h
Description
The
mkl_sparse_?_create_csc
 routine creates a handle for an
m
-by-
k
 matrix
A
 in CSC format.
The input arrays provided are left unchanged except for the call to mkl_sparse_order, which performs ordering of column indexes of the matrix. To avoid any changes to the input data, use mkl_sparse_copy.
Input Parameters
indexing
Indicates how input arrays are indexed.
SPARSE_INDEX_BASE_ZERO
Zero-based (C-style) indexing: indices start at 0.
SPARSE_INDEX_BASE_ONE
One-based (Fortran-style) indexing: indices start at 1.
rows
Number of rows of the matrix
A
.
cols
Number of columns of the matrix
A
.
cols_start
Array of length at least
m
. This array contains col indices, such that
cols_start
[
i
]
 -
ind
 is the first index of col
i
 in the arrays
values
 and
row_indx
.
ind
 takes 0 for zero-based indexing and 1 for one-based indexing.
Refer to
pointerB
 array description in CSC Format for more details.
cols_end
Array of at least length
m
. This array contains col indices, such that
cols_end
[
i
]
 -
ind
- 1
 is the last index of col
i
 in the arrays
values
 and
row_indx
.
ind
 takes 0 for zero-based indexing and 1 for one-based indexing.
Refer to
pointerE
 array description in CSC Format for more details.
row_indx
For one-based indexing, array containing the row indices plus one for each non-zero element of the matrix
A
. For zero-based indexing, array containing the row indices for each non-zero element of the matrix
A
. Its length is at least
cols_end
[
cols
 - 1]
 -
ind
.
ind
 takes 0 for zero-based indexing and 1 for one-based indexing.
values
Array containing non-zero elements of the matrix
A
. Its length is equal to length of the
row_indx
 array.
Refer to
values
 array description in CSC Format for more details.
Output Parameters
A
Handle containing internal data.
Return Values
The function returns a value indicating whether the operation was successful or not, and why.
SPARSE_STATUS_SUCCESS
The operation was successful.
SPARSE_STATUS_NOT_INITIALIZED
The routine encountered an empty handle or matrix array.
SPARSE_STATUS_ALLOC_FAILED
Internal memory allocation failed.
SPARSE_STATUS_INVALID_VALUE
The input parameters contain an invalid value.
SPARSE_STATUS_EXECUTION_FAILED
Execution failed.
SPARSE_STATUS_INTERNAL_ERROR
An error in algorithm implementation occurred.
SPARSE_STATUS_NOT_SUPPORTED
The requested operation is not supported.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804