Developer Reference for Intel® oneAPI Math Kernel Library - C

Developer Reference

  • 0.10
  • 10/21/2020
  • Public Content
Contents

mkl_?skymv

Computes matrix - vector product for a sparse matrix in the skyline storage format with one-based indexing (deprecated).

Syntax

void
mkl_sskymv
(
const
char
*transa
,
const
MKL_INT
*m
,
const
MKL_INT
*k
,
const
float
*alpha
,
const
char
*matdescra
,
const
float
*val
,
const
MKL_INT
*pntr
,
const
float
*x
,
const
float
*beta
,
float
*y
);
void
mkl_dskymv
(
const
char
*transa
,
const
MKL_INT
*m
,
const
MKL_INT
*k
,
const
double
*alpha
,
const
char
*matdescra
,
const
double
*val
,
const
MKL_INT
*pntr
,
const
double
*x
,
const
double
*beta
,
double
*y
);
void
mkl_cskymv
(
const
char
*transa
,
const
MKL_INT
*m
,
const
MKL_INT
*k
,
const
MKL_Complex8
*alpha
,
const
char
*matdescra
,
const
MKL_Complex8
*val
,
const
MKL_INT
*pntr
,
const
MKL_Complex8
*x
,
const
MKL_Complex8
*beta
,
MKL_Complex8
*y
);
void
mkl_zskymv
(
const
char
*transa
,
const
MKL_INT
*m
,
const
MKL_INT
*k
,
const
MKL_Complex16
*alpha
,
const
char
*matdescra
,
const
MKL_Complex16
*val
,
const
MKL_INT
*pntr
,
const
MKL_Complex16
*x
,
const
MKL_Complex16
*beta
,
MKL_Complex16
*y
);
Include Files
  • mkl.h
Description
This routine is deprecated. Use mkl_sparse_?_mvfrom the
Intel® oneAPI Math Kernel Library
 Inspector-executor Sparse BLAS interface instead.
The
mkl_?skymv
 routine performs a matrix-vector operation defined as 
y := alpha*A*x + beta*y
or 
y := alpha*A
T
*x + beta*y,
where:
alpha
 and
beta
 are scalars,
x
 and
y
 are vectors,
A
 is an
m
-by-
k
 sparse matrix stored using the skyline storage scheme,
A
T
 is the transpose of
A
.
This routine supports only one-based indexing of the input arrays.
Input Parameters
transa
Specifies the operation.
If
transa
 =
'N'
 or
'n'
, then
y
 :=
alpha
*
A
*
x
 +
beta
*
y
If
transa
 =
'T'
 or
't'
 or
'C'
 or
'c'
, then
y
 :=
alpha
*
A
T
*
x
 +
beta
*
y
,
m
Number of rows of the matrix
A
.
k
Number of columns of the matrix
A
.
alpha
Specifies the scalar
alpha
.
matdescra
Array of six elements, specifies properties of the matrix used for operation. Only first four array elements are used, their possible values are given in
Table “Possible Values of the Parameter
matdescra
 (
descra
)”
. Possible combinations of element values of this parameter are given in
Table “Possible Combinations of Element Values of the Parameter
matdescra
”
.
General matrices
(
matdescra
[0]
='G')
 is not supported.
val
Array containing the set of elements of the matrix
A
 in the skyline profile form.
If
matdescrsa
[1]
=
'L'
, then
val
 contains elements from the low triangle of the matrix
A
.
If
matdescrsa
[1]
=
'U'
, then
val
 contains elements from the upper triangle of the matrix
A
.
Refer to
values
 array description in Skyline Storage Scheme for more details.
pntr
Array of length
(
m
 + 1)
 for lower triangle, and
(
k
 + 1)
 for upper triangle.
It contains the indices specifying in the
val
 the positions of the first element in each row (column) of the matrix
A
. Refer to
pointers
 array description in Skyline Storage Scheme for more details.
x
Array, size at least
k
 if
transa
 =
'N'
 or
'n'
 and at least
m
 otherwise. On entry, the array
x
 must contain the vector
x
.
beta
Specifies the scalar
beta
.
y
Array, size at least
m
 if
transa
 =
'N'
 or
'n'
 and at least
k
 otherwise. On entry, the array
y
 must contain the vector
y
.
Output Parameters
y
Overwritten by the updated vector
y
.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804