Developer Reference for Intel® oneAPI Math Kernel Library - C

Developer Reference

  • 0.10
  • 10/21/2020
  • Public Content
Contents

?trttp

Copies a triangular matrix from the standard full format (TR) to the standard packed format (TP) .

Syntax

lapack_int
LAPACKE_strttp
(
int
matrix_layout
,
char
uplo
,
lapack_int
n
,
const
float
*
a
,
lapack_int
lda
,
float
*
ap
);
lapack_int
LAPACKE_dtrttp
(
int
matrix_layout
,
char
uplo
,
lapack_int
n
,
const
double
*
a
,
lapack_int
lda
,
double
*
ap
);
lapack_int
LAPACKE_ctrttp
(
int
matrix_layout
,
char
uplo
,
lapack_int
n
,
const
lapack_complex_float
*
a
,
lapack_int
lda
,
lapack_complex_float
*
ap
);
lapack_int
LAPACKE_ztrttp
(
int
matrix_layout
,
char
uplo
,
lapack_int
n
,
const
lapack_complex_double
*
a
,
lapack_int
lda
,
lapack_complex_double
*
ap
);
Include Files
  • mkl.h
Description
The routine copies a triangular matrix
A
 from the standard full format to the standard packed format.
Input Parameters
uplo
Specifies whether
A
 is upper or lower triangular:
= 'U': A is upper triangular,
= 'L': A is lower triangular.
n
The order of the matrix
A
,
n
≥
 0.
a
Array, size
max(1,
lda
*
n
)
.
On entry, the triangular matrix
A
. If
uplo
 = 'U', the leading
n
-by-
n
 upper triangular part of the array
a
 contains the upper triangular matrix, and the strictly lower triangular part of
a
 is not referenced. If
uplo
 = 'L', the leading
n
-by-
n
 lower triangular part of the array
a
 contains the lower triangular matrix, and the strictly upper triangular part of
a
 is not referenced.
lda
The leading dimension of the array
a.
lda
≥
max
(1,
n
).
Output Parameters
ap
Array, size at least
max
(1,
n
*(
n
+1)/2).
On exit, the upper or lower triangular matrix
A
, packed columnwise in a linear array. (see Matrix Storage Schemes)
Return Values
This function returns a value
info
.
If
info
 = 0
, the execution is successful.
If
info
 < 0
, the
i
-th parameter had an illegal value.
If
info
 = -1011
, memory allocation error occurred.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserverd for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804