Developer Reference

  • 0.9
  • 09/09/2020
  • Public Content
Contents

?trexc

Reorders the Schur factorization of a general matrix.

Syntax

lapack_int LAPACKE_strexc
(
int
matrix_layout
,
char
compq
,
lapack_int
n
,
float*
t
,
lapack_int
ldt
,
float*
q
,
lapack_int
ldq
,
lapack_int*
ifst
,
lapack_int*
ilst
);
lapack_int LAPACKE_dtrexc
(
int
matrix_layout
,
char
compq
,
lapack_int
n
,
double*
t
,
lapack_int
ldt
,
double*
q
,
lapack_int
ldq
,
lapack_int*
ifst
,
lapack_int*
ilst
);
lapack_int LAPACKE_ctrexc
(
int
matrix_layout
,
char
compq
,
lapack_int
n
,
lapack_complex_float*
t
,
lapack_int
ldt
,
lapack_complex_float*
q
,
lapack_int
ldq
,
lapack_int
ifst
,
lapack_int
ilst
);
lapack_int LAPACKE_ztrexc
(
int
matrix_layout
,
char
compq
,
lapack_int
n
,
lapack_complex_double*
t
,
lapack_int
ldt
,
lapack_complex_double*
q
,
lapack_int
ldq
,
lapack_int
ifst
,
lapack_int
ilst
);
Include Files
  • mkl.h
Description
The routine reorders the Schur factorization of a general matrix
A
=
Q*T*Q
H
, so that the diagonal element or block of
T
with row index
ifst
is moved to row
ilst
.
The reordered Schur form
S
is computed by an unitary (or, for real flavors, orthogonal) similarity transformation:
S
=
Z
H
*T*Z
. Optionally the updated matrix
P
of Schur vectors is computed as
P
=
Q*Z
, giving
A
=
P*S*P
H
.
Input Parameters
matrix_layout
Specifies whether matrix storage layout is row major (
LAPACK_ROW_MAJOR
) or column major (
LAPACK_COL_MAJOR
).
compq
Must be
'V'
or
'N'
.
If
compq
=
'V'
, then the Schur vectors (
Q
) are updated.
If
compq
=
'N'
, then no Schur vectors are updated.
n
The order of the matrix
T
(
n
0
).
t
,
q
Arrays:
t
(size max(1,
ldt
*
n
))
contains the
n
-by-
n
matrix
T
.
q
(size max(1,
ldq
*
n
))
If
compq
=
'V'
, then
q
must contain
Q
(Schur vectors).
If
compq
=
'N'
, then
q
is not referenced.
ldt
The leading dimension of
t
; at least max(1,
n
).
ldq
The leading dimension of
q
;
If
compq
=
'N'
, then
ldq
1
.
If
compq
=
'V'
, then
ldq
max(1,
n
)
.
ifst
,
ilst
1
ifst
n
; 1
ilst
n
.
Must specify the reordering of the diagonal elements (or blocks, which is possible for real flavors) of the matrix
T
. The element (or block) with row index
ifst
is moved to row
ilst
by a sequence of exchanges between adjacent elements (or blocks).
Output Parameters
t
Overwritten by the updated matrix
S
.
q
If
compq
=
'V'
,
q
contains the updated matrix of Schur vectors.
ifst
,
ilst
Overwritten for real flavors only.
If
ifst
pointed to the second row of a 2 by 2 block on entry, it is changed to point to the first row;
ilst
always points to the first row of the block in its final position (which may differ from its input value by
±
1).
Return Values
This function returns a value
info
.
If
info
=0
, the execution is successful.
If
info
=
-i
, the
i
-th parameter had an illegal value.
Application Notes
The computed matrix
S
is exactly similar to a matrix
T
+
E
, where
||
E
||
2
=
O
(
ε
)*||
T
||
2
, and
ε
is the machine precision.
Note that if a 2 by 2 diagonal block is involved in the re-ordering, its off-diagonal elements are in general changed; the diagonal elements and the eigenvalues of the block are unchanged unless the block is sufficiently ill-conditioned, in which case they may be noticeably altered. It is possible for a 2 by 2 block to break into two 1 by 1 blocks, that is, for a pair of complex eigenvalues to become purely real.
The approximate number of floating-point operations is
for real flavors:
6
n
(
ifst
-
ilst
)
if
compq
=
'N'
;
12
n
(
ifst
-
ilst
)
if
compq
=
'V'
;
for complex flavors:
20
n
(
ifst
-
ilst
)
if
compq
=
'N'
;
40
n
(
ifst
-
ilst
)
if
compq
=
'V'
.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804