Developer Reference for Intel® oneAPI Math Kernel Library - C

Developer Reference

  • 0.10
  • 10/21/2020
  • Public Content
Contents

?sbtrd

Reduces a real symmetric band matrix to tridiagonal form.

Syntax

lapack_int
LAPACKE_ssbtrd
(
int
matrix_layout
,
char
vect
,
char
uplo
,
lapack_int
n
,
lapack_int
kd
,
float
*
ab
,
lapack_int
ldab
,
float
*
d
,
float
*
e
,
float
*
q
,
lapack_int
ldq
);
lapack_int
LAPACKE_dsbtrd
(
int
matrix_layout
,
char
vect
,
char
uplo
,
lapack_int
n
,
lapack_int
kd
,
double
*
ab
,
lapack_int
ldab
,
double
*
d
,
double
*
e
,
double
*
q
,
lapack_int
ldq
);
Include Files
  • mkl.h
Description
The routine reduces a real symmetric band matrix
A
 to symmetric tridiagonal form
T
 by an orthogonal similarity transformation:
A
 =
Q*T*Q
T
. The orthogonal matrix
Q
 is determined as a product of Givens rotations.
If required, the routine can also form the matrix
Q
 explicitly.
Input Parameters
matrix_layout
Specifies whether matrix storage layout is row major (
LAPACK_ROW_MAJOR
) or column major (
LAPACK_COL_MAJOR
).
vect
Must be
'V'
,
'N'
, or
'U'
.
If
vect
 =
'V'
, the routine returns the explicit matrix
Q
.
If
vect
 =
'N'
, the routine does not return
Q
.
If
vect
 =
'U'
, the routine updates matrix
X
 by forming
X
*
Q
.
uplo
Must be
'U'
 or
'L'
.
If
uplo
 =
'U'
,
ab
 stores the upper triangular part of
A
.
If
uplo
 =
'L'
,
ab
 stores the lower triangular part of
A
.
n
The order of the matrix
A
 (
n
≥
0
).
kd
The number of super- or sub-diagonals in
A
(
kd
≥
0
).
ab
,
q
ab
(size at least max(1,
ldab
*
n
) for column major layout and at least max(1,
ldab
*(
kd
+ 1)) for row major layout)
 is an array containing either upper or lower triangular part of the matrix
A
 (as specified by
uplo
) in band storage format.
q
(size max(1,
ldq
*
n
))
 is an array.
If
vect
 =
'U'
, the
q
 array must contain an
n
-by-
n
 matrix
X
.
If
vect
 =
'N'
 or
'V'
, the
q
 parameter need not be set.
ldab
The leading dimension of
ab
; at least
kd
+1
for column major layout and
n
 for row major layout
 .
ldq
The leading dimension of
q
. Constraints:
ldq
≥
 max(1,
n
)
 if
vect
 =
'V'
 or
'U'
;
ldq
≥
 1
 if
vect
 =
'N'
.
Output Parameters
ab
On exit, the diagonal elements of the array
ab
 are overwritten by the diagonal elements of the tridiagonal matrix
T
. If
kd
 > 0, the elements on the first superdiagonal (if
uplo
 =
'U'
) or the first subdiagonal (if
uplo
 =
'L'
) are ovewritten by the off-diagonal elements of
T
. The rest of
ab
 is overwritten by values generated during the reduction.
d
,
e
,
q
Arrays:
d
 contains the diagonal elements of the matrix
T
.
The size of
d
 must be at least max(1,
n
).
e
 contains the off-diagonal elements of
T
.
The size of
e
 must be at least max(1,
n
-1).
q
 is not referenced if
vect
 =
'N'
.
If
vect
 =
'V'
,
q
 contains the
n
-by-
n
 matrix
Q
.
If
vect
 =
'U'
,
q
 contains the product
X
*
Q
.
Return Values
This function returns a value
info
.
If
info
=0
, the execution is successful.
If
info
 =
-i
, the
i
-th parameter had an illegal value.
Application Notes
The computed matrix
T
 is exactly similar to a matrix
A
+
E
, where
||
E
||
2
 =
c
(
n
)
*ε
*||
A
||
2
,
c
(
n
)
 is a modestly increasing function of
n
, and
ε
 is the machine precision. The computed matrix
Q
 differs from an exactly orthogonal matrix by a matrix
E
 such that
||
E
||
2
 =
O
(
ε
)
.
The total number of floating-point operations is approximately
6
n
2
*
kd
 if
vect
 =
'N'
, with
3
n
3
*(
kd
-1)/
kd
 additional operations if
vect
 =
'V'
.
The complex counterpart of this routine is hbtrd.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804