Developer Reference

  • 2021.1
  • 12/04/2020
  • Public Content

PBLAS Routines

Intel® oneAPI
Math Kernel Library
the PBLAS (Parallel Basic Linear Algebra Subprograms) routines from the ScaLAPACK package for distributed-memory architecture. PBLAS is intended for using in vector-vector, matrix-vector, and matrix-matrix operations to simplify the parallelization of linear codes. The design of PBLAS is as consistent as possible with that of the BLAS. The routine descriptions are arranged in several sections according to the PBLAS level of operation:
Each section presents the routine and function group descriptions in alphabetical order by the routine group name; for example, the
group, the
group. The question mark in the group name corresponds to a character indicating the data type (
, and
or their combination); see
Routine Naming Conventions
PBLAS routines are provided only with
Intel® oneAPI Math Kernel Library
versions for Linux* and Windows* OSs.
Generally, PBLAS runs on a network of computers using MPI as a message-passing layer and a set of prebuilt communication subprograms (BLACS), as well as a set of PBLAS optimized for the target architecture. The
Intel® oneAPI Math Kernel Library
version of PBLAS is optimized for Intel® processors. For the detailed system and environment requirements see
Intel® oneAPI Math Kernel Library
Release Notes
Intel® oneAPI Math Kernel Library
Developer Guide
For full reference on PBLAS routines and related information, see
Optimization Notice
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.
Notice revision #20110804
This notice covers the following instruction sets: SSE2, SSE4.2, AVX2, AVX-512.

Product and Performance Information


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