Developer Reference

  • 0.10
  • 10/21/2020
  • Public Content
Contents

p?lacp3

Copies from a global parallel array into a local replicated array or vice versa.

Syntax

void
pslacp3
(
const
MKL_INT
*
m
,
const
MKL_INT
*
i
,
float
*
a
,
const
MKL_INT
*
desca
,
float
*
b
,
const
MKL_INT
*
ldb
,
const
MKL_INT
*
ii
,
const
MKL_INT
*
jj
,
const
MKL_INT
*
rev
);
void
pdlacp3
(
const
MKL_INT
*
m
,
const
MKL_INT
*
i
,
double
*
a
,
const
MKL_INT
*
desca
,
double
*
b
,
const
MKL_INT
*
ldb
,
const
MKL_INT
*
ii
,
const
MKL_INT
*
jj
,
const
MKL_INT
*
rev
);
void pclacp3
(
const
MKL_INT
*
m
,
const
MKL_INT
*
i
,
MKL_Complex8
*
a
,
const
MKL_INT
*
desca
,
MKL_Complex8
*
b
,
const
MKL_INT
*
ldb
,
const
MKL_INT
*
ii
,
const
MKL_INT
*
jj
,
const
MKL_INT
*
rev
);
void pzlacp3
(
const
MKL_INT
*
m
,
const
MKL_INT
*
i
,
MKL_Complex16
*
a
,
const
MKL_INT
*
desca
,
MKL_Complex16
*
b
,
const
MKL_INT
*
ldb
,
const
MKL_INT
*
ii
,
const
MKL_INT
*
jj
,
const
MKL_INT
*
rev
);
Include Files
  • mkl_scalapack.h
Description
This is an auxiliary
function
that copies from a global parallel array into a local replicated array or vise versa. Note that the entire submatrix that is copied gets placed on one node or more. The receiving node can be specified precisely, or all nodes can receive, or just one row or column of nodes.
Optimization Notice
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.
Notice revision #20110804
This notice covers the following instruction sets: SSE2, SSE4.2, AVX2, AVX-512.
Input Parameters
m
(global)
m
is the order of the square submatrix that is copied.
m
0. Unchanged on exit.
i
(global)
The matrix element
A
(
i
,
i
) is the global location that the copying starts from. Unchanged on exit.
a
(local)
Array of size
lld_a
*
LOCc
(
n_a
)
. On entry, the parallel matrix to be copied into or from.
desca
(global and local) array of size
dlen_
. The array descriptor for the distributed matrix
A
.
b
(local)
Array of size
ldb
*
LOCc
(
m
)
. If
rev
= 0
, this is the global portion of the matrix
A
(
i
:
i
+
m
-1,
i
:
i
+
m
-1). If
rev
= 1
, this is unchanged on exit.
ldb
(local)
The leading dimension of
B
.
ii
,
jj
(global) By using
rev
0 and 1, data can be sent out and returned again. If
rev
= 0
, then
ii
is destination row index and
jj
is destination column index for the node(s) receiving the replicated
matrix
B
. If
ii
0,
jj
0, then node (
ii
,
jj
) receives the data. If
ii
= -1,
jj
0, then all rows in column
jj
receive the data. If
ii
0,
jj
= -1, then all cols in row
ii
receive the data. If
ii
= -1,
jj
= -1, then all nodes receive the data. If
rev
!=0, then
ii
is the source row index for the node(s) sending the replicated
B
.
rev
(global) Use
rev
= 0
to send global
matrix
A
into locally replicated
matrix
B
(on node (
ii
,
jj
)). Use
rev
!= 0 to send locally replicated
B
from node (
ii
,
jj
) to its owner (which changes depending on its location in
A
) into the global
A
.
Output Parameters
a
On exit, if
rev
= 1
, the copied data. Unchanged on exit if
rev
= 0
.
b
If
rev
= 1
, this is unchanged on exit.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserverd for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804