Developer Reference

  • 0.9
  • 09/09/2020
  • Public Content
Contents

p?lawil

Forms the Wilkinson transform.

Syntax

void
pslawil
(
const
MKL_INT
*
ii
,
const
MKL_INT
*
jj
,
const
MKL_INT
*
m
,
const
float
*
a
,
const
MKL_INT
*
desca
,
const
float
*
h44
,
const
float
*
h33
,
const
float
*
h43h34
,
float
*
v
);
void
pdlawil
(
const
MKL_INT
*
ii
,
const
MKL_INT
*
jj
,
const
MKL_INT
*
m
,
const
double
*
a
,
const
MKL_INT
*
desca
,
const
double
*
h44
,
const
double
*
h33
,
const
double
*
h43h34
,
double
*
v
);
void
pclawil
(
const
MKL_INT
*
ii
,
const
MKL_INT
*
jj
,
const
MKL_INT
*
m
,
const
MKL_Complex8
*
a
,
const
MKL_INT
*
desca
,
const
MKL_Complex8
*
h44
,
const
MKL_Complex8
*
h33
,
const
MKL_Complex8
*
h43h34
,
MKL_Complex8
*
v
);
void
pzlawil
(
const
MKL_INT
*
ii
,
const
MKL_INT
*
jj
,
const
MKL_INT
*
m
,
const
MKL_Complex16
*
a
,
const
MKL_INT
*
desca
,
const
MKL_Complex16
*
h44
,
const
MKL_Complex16
*
h33
,
const
MKL_Complex16
*
h43h34
,
MKL_Complex16
*
v
);
Include Files
  • mkl_scalapack.h
Description
The
p?lawil
function
gets the transform given by
h44
,
h33
, and
h43h34
into
v
starting at row
m
.
Input Parameters
ii
(global)
Number of the process row which owns the matrix element
A
(
m
+2,
m
+2).
jj
(global)
Number of the process column which owns the matrix element
A
(
m
+2,
m
+2).
m
(global)
On entry, the location from where the transform starts (row
m
). Unchanged on exit.
a
(local)
Array of size
lld_a
*
LOCc
(
n_a
)
.
On entry, the Hessenberg matrix. Unchanged on exit.
desca
(global and local)
Array of size
dlen_
. The array descriptor for the distributed matrix
A
. Unchanged on exit.
h44
,
h33
,
h43h34
(global)
These three values are for the double shift
QR
iteration. Unchanged on exit.
Output Parameters
v
(global)
Array of size 3 that contains the transform on output.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804