Developer Reference

  • 0.9
  • 09/09/2020
  • Public Content
Contents

pilaenv

Returns the positive integer value of the logical blocking size.

Syntax

MKL_INT
pilaenv
(
const MKL_INT
*ictxt
,
const char
*prec
);
Include Files
  • mkl_pblas.h
Description
pilaenv
returns the positive integer value of the logical blocking size. This value is machine and precision specific. This version provides a logical blocking size which should give good though not optimal performance on many of the currently available distributed-memory concurrent computers. You are encouraged to modify this subroutine to set this tuning parameter for your particular machine.
Input Parameters
ictxt
On entry,
ictxt
specifies the BLACS context handle, indicating the global context of the operation. The context itself is global, but the value of
ictxt
is local.
prec
On input,
prec
specifies the precision for which the logical block size should be returned as follows:
prec
= 'S' or 's'
single precision real,
prec
= 'D' or 'd'
double precision real,
prec
= 'C' or 'c'
single precision complex,
prec
= 'Z' or 'z'
double precision complex,
prec
= 'I' or 'i'
integer.
Application Notes
Before modifying this routine to tune the library performance on your system, be aware of the following:
  1. The value this function returns must be strictly larger than zero,
  2. If you are planning to link your program with different instances of the library (for example, on a heterogeneous machine), you
    must
    compile each instance of the library with exactly the same version of this routine for obvious interoperability reasons.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804