BRNG Parameter Definition
Predefined values for the
brng
input
parameter are as follows:
Value
| Short Description
|
|---|---|
VSL_BRNG_MCG31 | A 31-bit multiplicative congruential generator.
|
VSL_BRNG_R250 | A generalized feedback shift register
generator.
|
VSL_BRNG_MRG32K3A | A combined multiple recursive generator with
two components of order 3.
|
VSL_BRNG_MCG59 | A 59-bit multiplicative congruential generator.
|
VSL_BRNG_WH | A set of 273 Wichmann-Hill combined
multiplicative congruential generators.
|
VSL_BRNG_MT19937 | A Mersenne Twister pseudorandom number
generator.
|
VSL_BRNG_MT2203 | A set of 6024 Mersenne Twister pseudorandom
number generators.
|
VSL_BRNG_SFMT19937 | A SIMD-oriented Fast Mersenne Twister
pseudorandom number generator.
|
VSL_BRNG_SOBOL | A 32-bit Gray code-based generator producing
low-discrepancy sequences for dimensions
1
; user-defined dimensions are also available.
≤ s
≤
40 |
VSL_BRNG_NIEDERR | A 32-bit Gray code-based generator producing
low-discrepancy sequences for dimensions
1
; user-defined dimensions are also available.
≤ s
≤
318 |
VSL_BRNG_IABSTRACT | An abstract random number generator for integer
arrays.
|
VSL_BRNG_DABSTRACT | An abstract random number generator for double
precision floating-point arrays.
|
VSL_BRNG_SABSTRACT | An abstract random number generator for single
precision floating-point arrays.
|
VSL_BRNG_NONDETERM | A non-deterministic random number generator.
|
VSL_BRNG_PHILOX4X32X10 | A Philox4x32-10 counter-based pseudorandom
number generator.
|
VSL_BRNG_ARS5 | An ARS-5 counter-based pseudorandom number
generator that uses instructions from the AES-NI set.
|
See
VS Notes for detailed
description.
Optimization Notice
|
|---|
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.
Notice revision #20110804
|
This notice covers the following instruction sets: SSE2, SSE4.2, AVX2, AVX-512.