Developer Guide for Intel® oneAPI Math Kernel Library for Linux*

Developer Guide

  • 2021.1
  • 12/04/2020
  • Public Content
Contents

Specifying Code Branches

Intel® oneAPI Math Kernel Library
 provides a conditional numerical reproducibility (CNR) functionality that enables you to obtain reproducible results from oneMKL routines. When enabling CNR, you choose a specific code branch of
Intel® oneAPI Math Kernel Library
 that corresponds to the instruction set architecture (ISA) that you target. You can specify the code branch and other CNR options using the
MKL_CBWR
 environment variable.
  • MKL_CBWR="
    <branch>[,STRICT]
    "
     or
  • MKL_CBWR="BRANCH=
    <branch>[,STRICT]
    "
Use the
STRICT
 flag to enable strict CNR mode. For more information, see Reproducibility Conditions.
The
<branch>
 placeholder specifies the CNR branch with one of the following values:
Value
Description
AUTO
CNR mode uses the standard ISA-based dispatching model while ensuring fixed cache sizes, deterministic reductions, and static scheduling
COMPATIBLE
Intel® Streaming SIMD Extensions 2 (Intel® SSE2) without rcpps/rsqrtps instructions
SSE2
Intel SSE2
SSE3
DEPRECATED.
Intel® Streaming SIMD Extensions 3 (Intel® SSE3)
. This setting is kept for backward compatibility and is equivalent to
SSE2
.
SSSE3
Supplemental Streaming SIMD Extensions 3 (SSSE3)
SSE4_2
Intel® Streaming SIMD Extensions 4.2 (Intel® SSE4.2)
AVX
Intel® Advanced Vector Extensions (Intel® AVX)
AVX2
Intel® Advanced Vector Extensions 2 (Intel® AVX2)
AVX512
Intel AVX-512 on Intel® Xeon® processors
AVX512_E1
Intel® Advanced Vector Extensions 512 (Intel® AVX-512) with support for Vector Neural Network Instructions
AVX512_MIC
Intel® Advanced Vector Extensions 512 (Intel® AVX-512) on Intel® Xeon Phi™ processors
AVX512_MIC_E1
Intel® Advanced Vector Extensions 512 (Intel® AVX-512) with support for Vector Neural Network Instructions on Intel® Xeon Phi™ processors
When specifying the CNR branch, be aware of the following:
  • Reproducible results are provided under Reproducibility Conditions.
  • Settings other than
    AUTO
     or
    COMPATIBLE
     are available only for Intel processors.
  • To get the CNR branch optimized for the processor where your program is currently running, choose the value of
    AUTO
     or call the
    mkl_cbwr_get_auto_branch
     function.
  • Strict CNR mode is only supported for AVX2, AVX512, AVX512_E1, AVX512_MIC, and AVX512_MIC_E1 branches. You can also use strict CNR mode with the AUTO branch when running on Intel processors that support one of these instruction set architectures (ISAs).
Setting the
MKL_CBWR
 environment variable or a call to an equivalent
mkl_cbwr_set
 function fixes the code branch and sets the reproducibility mode.
  • If the value of the branch is incorrect or your processor or operating system does not support the specified ISA, CNR ignores this value and uses the
    AUTO
     branch without providing any warning messages.
  • Calls to functions that define the behavior of CNR must precede any of the math library functions that they control.
  • Settings specified by the functions take precedence over the settings specified by the environment variable.
See the
Intel® oneAPI Math Kernel Library
 Developer Reference
 for how to specify the branches using functions.
Optimization Notice
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.
Notice revision #20110804
This notice covers the following instruction sets: SSE2, SSE4.2, AVX2, AVX-512.

Product and Performance Information

1

Performance varies by use, configuration and other factors. Learn more at www.Intel.com/PerformanceIndex.