Interaction with the Message-passing Interface
To improve performance of cluster applications, it is critical for
to use the optimal number of threads, as well as the correct thread affinity. Usually, the optimal number is the number of available cores per node divided by the number of MPI processes per node. You can set the number of threads using one of the available methods, described inTechniques to Set the Number of Threads.
Intel® oneAPI Math Kernel Library
If the number of threads is not set,
checks whether it runs under MPI provided by the Intel® MPI Library. If this is true, the following environment variables define
threading behavior:
Intel® oneAPI Math Kernel Library
Intel® oneAPI Math Kernel Library
- I_MPI_THREAD_LEVEL
- MKL_MPI_PPN
- I_MPI_NUMBER_OF_MPI_PROCESSES_PER_NODE
- I_MPI_PIN_MAPPING
- OMPI_COMM_WORLD_LOCAL_SIZE
- MPI_LOCALNRANKS
The threading behavior depends on the value of
I_MPI_THREAD_LEVEL
as follows:
- 0 or undefined.considers that thread support level of Intel MPI Library isIntel® oneAPI Math Kernel LibraryMPI_THREAD_SINGLEand defaults to sequential execution.
- 1, 2, or 3.This value determinesconclusion of the thread support level:Intel® oneAPI Math Kernel Library
- 1 -MPI_THREAD_FUNNELED
- 2 -MPI_THREAD_SERIALIZED
- 3 -MPI_THREAD_MULTIPLE
In all these cases,determines the number of MPI processes per node using the other environment variables listed and defaults to the number of threads equal to the number of available cores per node divided by the number of MPI processes per node.Intel® oneAPI Math Kernel Library
Instead of relying on the discussed implicit settings, explicitly set the number of threads for
.
Intel® oneAPI Math Kernel Library
Optimization Notice
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Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.
Notice revision #20110804
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This notice covers the following instruction sets: SSE2, SSE4.2, AVX2, AVX-512.