• 04/03/2020
  • Public Content

Scheduling Individual Nodes to Different Targets

OpenVINO™ toolkit supports OpenVX* 1.1 “target” API for assigning individual nodes of an OpenVX graph to a particular target, overriding run-time defaults. This enables heterogeneous usages of Intel platforms for better hardware utilization.
You might want to schedule nodes to a particular target to improve performance or power consumption. Also, if there is enough parallelism in the graph, multiple branches of the graph (like individual RGB channels) can be scheduled to the different targets and then execute simultaneously.
NOTE: For detailed information and code examples for the Targets API, refer to the
OpenVX Heterogeneous Basic Sample
, located at the
NOTE: As discussed previously, only CPU and GPU are supported as full-blown targets.
NOTE: Intel® MKL powered implementation of the CNN kernels for the CPU constitutes a separated target "mkldnn". The recommended order of targets for graphs with CNN nodes is following:
$ export VX_INTEL_ALLOWED_TARGETS="cpu,mkldnn,gpu"
The following code snippet illustrates the target API in action:
// Instantiate a node in a graph and set its target node = vxAccumulateImageNode(graph, input, output); status = vxSetNodeTarget(node, VX_TARGET_GPU_INTEL, NULL); if (status == VX_ERROR_NOT_SUPPORTED) { // the node is not supported by the target // so the vxAssignNodeAffinity had no effect // and the implementation falls back to the default target }
NOTE: All calls to the
for nodes of a graph should happen before
for this graph.
Following are the important considerations for setting nodes affinities:
  • If no target is specified for a node, it will be targeted to run on the CPU
  • If setting a target fails (for example, if node is not supported by the given target), the implementation will fall back to the default target (CPU).

Product and Performance Information


Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804